TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME N1 SCL0 U9 VSS N2 SDA0 U10 CVDD N3 ED31 U11 CVDD N4 VSS U12 DVDD N17 VSS U13 VSS N18 ED6 U14 CVDD N19 ED7 U15 CVDD N20 ED8 U16 DVDD P1 ED28 U17 VSS P2 ED29 U18 EA21 P3 ED30 U19 BE1 P4 VSS U20 VSS P17 VSS V1 ED20 P18 ED9 V2 ED19 P19 VSS V3 CVDD P20 ED10 V4 ED16 R1 DVDD V5 BE3 R2 ED27 V6 CE3 R3 ED26 V7 EA3 R4 CVDD V8 EA5 R17 CVDD V9 EA8 R18 DVDD V10 EA10 R19 ED11 V11 ARE/SDCAS/SSADS R20 ED12 V12 AWE/SDWE/SSWE T1 ED24 V13 DVDD T2 ED25 V14 EA12 T3 DVDD V15 DVDD T4 VSS V16 EA17 T17 VSS V17 CE0 T18 ED13 V18 CVDD T19 ED15 V19 DVDD T20 ED14 V20 BE0 U1 ED22 W1 VSS U2 ED21 W2 CVDD U3 ED23 W3 DVDD U4 VSS W4 ED17 U5 DVDD W5 VSS U6 CVDD W6 CE2 U7 DVDD W7 EA4 U8 VSS W8 EA6 Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME W9 DVDD Y5 ARDY W10 AOE/SDRAS/SSOE Y6 EA2 W11 VSS Y7 DVDD W12 DVDD Y8 EA7 W13 EA11 Y9 EA9 W14 EA13 Y10 ECLKOUT W15 EA15 Y11 ECLKIN W16 VSS Y12 CLKOUT2/GP[2] W17 EA19 Y13 VSS W18 CE1 Y14 EA14 W19 CVDD Y15 EA16 W20 VSS Y16 EA18 Y1 VSS Y17 DVDD Y2 VSS Y18 EA20 Y3 ED18 Y19 VSS Y4 BE2 Y20 VSS Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 7: SPRS294A − OCTOBER 2005 − REVIS
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60:
SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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SPRS294A − OCTOBER 2005 − REVIS
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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