TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 general-purpose input/output (GPIO) To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured. GPxEN = 1 GP[x] pin is enabled GPxDIR = 0 GP[x] pin is an input GPxDIR = 1 GP[x] pin is an output where “x” represents one of the 15 through 0 GPIO pins Figure 18 shows the GPIO enable bits in the GPEN register for the C6713B device. To use any of the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default values are device-specific, so refer to Figure 18 for the C6713B default configuration. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 EN GP14 EN GP13 EN GP12 EN GP11 EN GP10 EN GP9 EN GP8 EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 GP7 EN Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset GP6 EN GP5 EN GP4 EN GP3 EN Figure 18. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] GP2 EN GP1 EN GP0 EN Figure 19 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By default, all the GPIO pins are configured as input pins. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 DIR GP14 DIR GP13 DIR GP12 DIR GP11 DIR GP10 DIR GP9 DIR GP8 DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7 DIR Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset GP6 DIR GP5 DIR GP4 DIR GP3 DIR Figure 19. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] GP2 DIR GP1 DIR GP0 DIR For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). 90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 power-down mode logic Figure 20 shows the power-down mode logic on the C6713B. CLKOUT2 Internal Clock Tree Clock Distribution and Dividers PD1 PD2 Clock PLL Power- Down Logic PWRD IFR IER CSR Internal Peripherals CPU PD3 <strong>TMS320C6713B</strong> CLKIN RESET † External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic. triggering, wake-up, and effects Figure 20. Power-Down Mode Logic † The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 21 and described in Table 44. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when “writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 91
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTICHANNEL BUFFERED SERIAL PORT T
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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