European Patent Bulletin 2012/36 - European Patent Office
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European Patent Bulletin 2012/36 - European Patent Office

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(H05B) I.1(2)<br />

H05B 37/02 → (51) H01S 5/0683<br />

H05B 37/02 → (51) H04N 7/15<br />

H05B 39/08 → (51) H05B 37/02<br />

H05H 1/46 → (51) C23C 16/511<br />

H05K 1/00 → (51) H01L 51/00<br />

H05K 1/09 → (51) H01B 5/00<br />

(51) H05K 1/16 (11) 2 496 059 A2<br />

(25) En (26) En<br />

(21) 12158054.2 (22) 05.03.<strong>2012</strong><br />

(84) AL AT BE BG CH CY CZ DE DK EE ES FI FR<br />

GB GR HR HU IE IS IT LI LT LU LV MC MK<br />

MT NL NO PL PT RO RS SE SI SK SM TR<br />

BA ME<br />

(30) 04.03.2011 US 201113040841<br />

(54) Platinen-eingebetteter Kondensator mit<br />

mehreren Platten und Verfahren zu seiner<br />

Herstellung<br />

Multi-plate board-embedded capacitor and<br />

methods for fabricating the same<br />

Condensateur intégré au panneau multiplaques<br />

et procédés de fabrication de<br />

celui-ci<br />

(71) General Electric Company, 1 River Road,<br />

Schenectady, NY 12345, US<br />

(72) Abawi, Daniel Z., Minden, NV 89423-4119,<br />

US<br />

(74) Picker, Madeline Margaret, et al, GE International<br />

Inc. Global <strong>Patent</strong> Operation - Europe<br />

15 John Adam Street, London WC2N 6LU,<br />

GB<br />

(51) H05K 1/18 (11) 2 496 060 A1<br />

H01R 9/00<br />

(25) Ja (26) En<br />

(21) 10826344.3 (22) 28.10.2010<br />

(84) AL AT BE BG CH CY CZ DE DK EE ES FI FR<br />

GB GR HR HU IE IS IT LI LT LU LV MC MK<br />

MT NL NO PL PT RO RS SE SI SK SM TR<br />

(86) JP 2010/006372 28.10.2010<br />

(87) WO 2011/052208 2011/18 05.05.2011<br />

(30) 29.10.2009 JP 2009248492<br />

(54) LEITERPLATTENEINHEIT<br />

WIRING BOARD UNIT<br />

UNITÉ À PLAQUETTE DE CIRCUIT<br />

IMPRIMÉ<br />

(71) Daikin Industries, Ltd., Umeda Center Bldg.,<br />

4-12, Nakazaki-Nishi 2-chome Kita-ku,<br />

Osaka-shi, Osaka 530-8323, JP<br />

(72) KAGIMURA, Sumio, Sakai-shi Osaka 591-<br />

8511, JP<br />

DOUMAE, Hiroshi, Sakai-shi Osaka 591-<br />

8511, JP<br />

(74) HOFFMANN EITLE, <strong>Patent</strong>- und Rechtsanwälte<br />

Arabellastrasse 4, 81925 München,<br />

DE<br />

H05K 3/18 → (51) H05K 3/34<br />

H05K 3/32 → (51) H01B 5/00<br />

(51) H05K 3/34 (11) 2 496 061 A1<br />

H01L 23/12 H05K 3/18<br />

H05K 3/38<br />

(25) Ja (26) En<br />

(21) 10826347.6 (22) 28.10.2010<br />

(84) AL AT BE BG CH CY CZ DE DK EE ES FI FR<br />

GB GR HR HU IE IS IT LI LT LU LV MC MK<br />

MT NL NO PL PT RO RS SE SI SK SM TR<br />

(86) JP 2010/006378 28.10.2010<br />

(87) WO 2011/052211 2011/18 05.05.2011<br />

(30) 30.10.2009 JP 2009251378<br />

30.10.2009 JP 2009251269<br />

04.11.2009 JP 2009253130<br />

Europäisches <strong>Patent</strong>blatt<br />

<strong>European</strong> <strong>Patent</strong> <strong>Bulletin</strong><br />

<strong>Bulletin</strong> européen des brevets<br />

04.11.2009 JP 2009253501<br />

04.11.2009 JP 2009253502<br />

(54) LEITERPLATTE UND HALBLEITERVOR-<br />

RICHTUNG MIT EINER AUF EINER LEI-<br />

TERPLATTE MONTIERTEN KOMPONENTE<br />

CIRCUIT BOARD, AND SEMICONDUCTOR<br />

DEVICE HAVING COMPONENT MOUNTED<br />

ON CIRCUIT BOARD<br />

CARTE DE CIRCUIT IMPRIMÉ ET DISPO-<br />

SITIF À SEMI-CONDUCTEURS COMPRE-<br />

NANT UN COMPOSANT MONTÉ SUR UNE<br />

CARTE DE CIRCUIT IMPRIMÉ<br />

(71) Panasonic Corporation, 1006, Oaza Kadoma<br />

Kadoma-shi, Osaka 571-8501, JP<br />

(72) YOSHIOKA, Shingo, Osaka-shi Osaka 540-<br />

6207, JP<br />

FUJIWARA, Hiroaki, Osaka-shi Osaka 540-<br />

6207, JP<br />

TAKASHITA, Hiromitsu, Osaka-shi Osaka<br />

540-6207, JP<br />

TAKEDA, Tsuyoshi, Osaka-shi Osaka 540-<br />

6207, JP<br />

(74) Schwabe - Sandmair - Marx, <strong>Patent</strong>anwälte<br />

Stuntzstraße 16, 81677 München, DE<br />

H05K 3/34 → (51) H01B 5/00<br />

H05K 3/<strong>36</strong> → (51) H01R 11/01<br />

H05K 3/38 → (51) H05K 3/34<br />

(51) H05K 3/44 (11) 2 496 062 A1<br />

(25) En (26) En<br />

(21) 12003710.6 (22) 19.05.2008<br />

(84) AT BE BG CH CY CZ DE DK EE ES FI FR GB<br />

GR HR HU IE IS IT LI LT LU LV MC MT NL<br />

NO PL PT RO SE SI SK TR<br />

(30) 11.06.2007 US 760804<br />

(54) Verfahren zur Ausbildung von festen<br />

Blinddurchgängen durch den dielektrischen<br />

Überzug auf Substratmaterialien<br />

hochintegrierter Schaltungen (HDI)<br />

Method of forming solid blind vias<br />

through the dielectric coating on high<br />

density interconnect (HDI) substrate<br />

materials<br />

Procédé de formation de trous de raccordement<br />

de volets solides à travers le<br />

revêtement diélectrique sur des matériaux<br />

de substrat d'interconnexion haute densité<br />

(71) PPG Industries Ohio, Inc., 3800 West 143rd<br />

Street, Cleveland, OH 44111, US<br />

(72) Wang, Alan, E., Pitsburgh PA 15272, US<br />

Olson, Kevin C., Wexford Pennsylvania<br />

15090, US<br />

(74) Polypatent, Braunsberger Feld 29, 51429<br />

Bergisch Gladbach, DE<br />

(62) 08755835.9 / 2 163 147<br />

H05K 5/00 → (51) B60C 23/04<br />

H05K 7/00 → (51) H01R 9/22<br />

378<br />

Anmeldungen<br />

Applications<br />

Demandes (<strong>36</strong>/<strong>2012</strong>) 05.09.<strong>2012</strong>

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