Semiconductor Equipment - Berenberg Bank

Semiconductor Equipment
Technology Hardware
Where are chip-makers spending?
The semiconductor equipment vendors usually specialise in tools used in either one
or more chip fabrication steps. In Figure 23, we lay out the exposures of different
equipment suppliers within the chip fabrication process, and their relative market
share in wafer fab equipment capex. The total wafer fab equipment capex was
$38bn in 2012 – 81% of total capex.
Figure 23: Chip fabrication process
Silicon ingots up to 300mm in diameter
Ingots sliced into wafer and polished
ShinEtsu, Sumco, Siltronic
Deposition: $6bn market (15.7% total semi equipment)
AMAT 47%, TEL 12%, LAM 11%, ASMI 5%
Grows, coats or transfer a material onto wafer, known as thin film deposition. Eg:
SiO 2 which is widely used. (the yellow layer in pic) Performed by CVD/Pasma/PVD
treatment systems.
Si Wafer
Photoresist processing - Coating:
$1.6bn market (4.2%)
TEL 89%, Dainippon 7%, Suss 1%
Wafer is coated with chemical photoresist, thus pattern on
photomask transferred to wafer surface after exposure.
Photoresist:
JSR, TOK,RHEM,ShinEtsu
Chemical photoresist.
SiO 2
SiO 2
Photoresist
Lightsource:
Cymer, Gigaphoton, Ushio
Si Wafer
Lithography:
$6.5bn market (17.2%)
ASML 74%, Nikon 17%, Canon 2%
Wafer coated with photoresist exposed by
litho tool (machine focuses, aligns, and
moves the mask).
Photoresist processing - Development:
$1.6bn market (4.2%)
TEL 89%, Dainippon 7%, Suss 1%
Exposed region of wafer washed away by chemical, areas of with and without
photoresist produce the pattern from mask. Performed by Coater/developers.
Etching:
$7.5bn market (incl clean, Planarization), (19.5%)
LAM 29%. TEL 22%, Dainippon 18%, AMAT 12%
The thin film layer from ‘Deposition’ not covered by photoresist is etched away, to
permanently transfer pattern to wafer surface. Performed by Etch systems.
Doping:
$1.0bn market (2.7%) AMAT 76%, SEN 10%,
Introduces atoms of elements into silicon to alter the electrical properties in the
silicon dioxide free areas, forming transistors.
Photoresist stripping:
$0.2bn market (0.1%) Mattson 20%, PSK 19%, LAM 17%
Remaining photoresist is removed from etched wafer.
Part of lithography tools.
Photomask:
DNP, Toppanm
To create 1-1 correspondence on
wafer through litho.
Develop
Etching
Doping
DP:
The steps from PR coating to PR stripping repeats to
scale IC further scale to 20nm and beyond:
10-100 layers will be constructed on single
wafer
Wafer level Testing
Market Size $0.2bn, (0.1%) TEL 39%, Seimitsu 48%
Performed before on wafer by wafer probe.
Chips Packing:
Market Size $3.9bn, (10.1%)
Kulicke 19%, ASMP 16%
Wafer is sliced to Dies, and packaged to become chips
Wafer level Packing:
Market Size $1.4bn, (3.0%)
Mattson 20%, EV 6%, Ultratech 5%, Suss 4%
Packaging an IC at wafer level before dicing.
Source: Nikon, Berenberg data, Gartner data
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