Semiconductor Equipment - Berenberg Bank

Semiconductor Equipment
Technology Hardware
We believe the lithography, process control, and wafer level packaging markets
have the biggest growth potential, driven by node shrinkage and 3D packaging
demand, hence ASML, KLA and SUSS are likely to outperform other equipment
suppliers. We do not like the etching, deposition and die level packaging markets
because their growth potential is limited as a result of technology migration.
Figure 24: Capex on fabrication steps/total semiconductor capex
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
2009 2010 2011 2012 2016E
Deposition Photoresist Processing Lithography
Etch, Clean and Planarization Doping Automation
Process Control Wafer-Level Packaging Die-Level Packaging
Test Equipment
Source: Gartner data
Figure 24 shows that deposition, lithography and etching and cleaning are the only
three process categories that individually account for more than 10% of total
semiconductor capex. The combined capex for these three categories was 34% of
total semiconductor capex in 2012. We expect the combined share of capex to
expand to 38% in 2016, driven mainly by lithography growth. Wafer level
packaging, due to its small base, has since 2003 seen the fastest growth at c10% per
annum, compared with c2.6% for total semiconductor capex.
Lithography – expanding market and ASML as monopolist
During the past decade, the lithography market has grown by c1.7% per year, while
total semiconductor capex has grown by 2.6% annually. Looking ahead to 2016, we
estimate that the lithography market will grow at c20%, four times faster than total
semiconductor capex. At a result, we estimate that lithography’s share of
semiconductor capex will expand to 20% in 2016 from 12% today.
As the chip-makers shrink from the 28nm mainstream node today to sub-10nm
over the next three to four years, the demand for lithography is likely to increase
significantly. According to TSMC, Intel and Samsung’s roadmaps, we believe 20nm
will be the mainstream node for logic and foundry in 2013/2014, which is likely to
be manufactured using the double patterning (DB) process. As a result, demand for
the most advanced argon-fluoride (ArFi) tools will double, and methodology tools
will also be needed to maintain an acceptable yield rate. Beyond 20nm, chip-makers
may adopt EUV or triple/quadruple patterning using ArFi tools, but in both cases
the lithography cost will increase significantly. The reason for this is that EUV may
cost €100m each versus ArFi costs of €40m, and triple/quadruple patterning may
need three to four times as many ArFi tools compared with single-patterning,
which is currently used in 28nm.
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