Semiconductor Equipment - Berenberg Bank
Semiconductor Equipment - Berenberg Bank
Semiconductor Equipment - Berenberg Bank
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ASML Holding NV<br />
Technology Hardware<br />
We believe 2016 shipments will be strong as chip-makers will start to allocate more<br />
layers to EUV as they gain more experience of the technology, and because<br />
DP/MP is currently too complex/expensive to be used in 20nm/10nm mass<br />
production.<br />
Our assumptions for tools shipped are based on our end market analysis (see<br />
Figure 8 below).<br />
Our assumptions are as follows.<br />
• Foundry/logic players (excluding Intel) will reach 340,000wpm 28nm<br />
and 60,000wpm 20nm/16nm capacity in 2013, and will continuously<br />
expand 20/16nm wafer capacity to reach 270,000wpm in 2016, which is<br />
less than 28nm capacity today: TSMC stated that 20/16nm could be a bigger<br />
node compared to 28nm. We have taken a conservative approach in making<br />
our 20/16nm capacity assumption, as TSMC may re-use equipment from 28nm<br />
if it ramps up aggressively on 20/16nm. We estimate that 10nm capacity will<br />
begin to ramp up from 2016 and reach 20,000wpm in 2016. We included four<br />
EUV R&D tools in our analysis and assigned €70m ASP for each of them,<br />
which is lower than the normal EUV ASP of €100m.<br />
• DRAM starts to adopt EUV in 2015, and migrates 53% of total wafer<br />
capacity to 30nm and below in 2016: We have been conservative here to<br />
reflect the memory spending pause. DRAM-makers plan to shift 69% capacity<br />
to 30nm or less, according to their various statements. We included two EUV<br />
R&D tools in our analysis, with an ASP of €70m each.<br />
• NAND starts to adopt EUV in 2016, and migrates 65% of total wafer<br />
capacity to 20nm and below in 2016: We have taken a conservative approach<br />
on NAND, too, to take account of the expected memory spending pause.<br />
NAND-makers plan to shift 83% capacity to 20nm or less, according to their<br />
various statements.<br />
3D NAND is less lithography intensive compared to 20nm/10nm NAND<br />
design. Our analysis suggests the impact of 3D NAND on total capex is likely<br />
to be small. We estimate that the maximum negative impact on EUV demand<br />
by 3D NAND is 3 EUV tools.<br />
• Intel will have 85,000wpm capacity on 22nm and 33,000wpm on 14/10nm<br />
in 2016, and it will re-use ArFi tools in 2014 when 14nm/10nm first ramps up.<br />
• In terms of market share, we assume ASML to have:<br />
o 100% of the EUV order from all chip-makers;<br />
o 100% of the ArFi/ArF tool order from foundry/logic (excluding Intel),<br />
DRAM and NAND players;<br />
o 60% of the KrF/I Line tool orders from foundry/logic (excluding Intel),<br />
DRAM and NAND players;<br />
o 60% of the ArFi,/ArF tool orders from Intel;<br />
o 50% of the KrF/I Line tool order from Intel.<br />
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