Semiconductor Equipment - Berenberg Bank

Suess Microtec AG
Small/Mid-Cap: Technology Hardware
Small, but active in growing markets
SUSS is heavily exposed to various growing end-markets, including MEMS, 3D
integration and EUV lithography equipment. It supplies equipment used by
packaging/assembling companies, MEMS manufacturers, integrated device
manufacturers (IDMs) and lithography photomask shops. It has optimised its endmarket
exposure through various acquisitions and disposals over the past few years.
3D bonding – revenue may triple in 2016/2017
The hottest topic in the semiconductor industry today is how to deliver smaller
chips with less power consumption, better performance and more functionality.
Shrinking the size of chips used to be the only solution adopted by chip-makers. As
current chip design is likely to approach its physical limits at 7nm/5nm, 3D
integration is viewed as the most feasible way to continue delivering smaller chips.
Yole Development expects the bonding market to grow from $150m today to
$500m-1bn once volume adoption starts – therefore SUSS’s bonder revenue may
triple from €30m to €100m in 2016/17.
Stacking, which can be done at the die or wafer level, is one of the key primary
technologies that enables 3D integration. It works by vertically stacking individual
chip components and interconnecting them by means of TSV (through-silicon via)
(see Figure 2 below). Shorter signal paths, reduced power consumption, enhanced
bandwidths and smaller surface areas can be achieved by stacking dies or wafers on
top of each other.
Figure 2: 3D stacking and TSV
Source:www.nist.gov
Source: electronicsbus.com
SUSS has received two orders from a leading IDM (Samsung we believe) for 3D
bonders to build its 3D pilot line. If Samsung releases a sample chip next year, the
remaining chip-makers are very likely to follow suit. Due to the high level of
competition, chip-makers will want to remain diversified and become involved in
all possible mainstream chip designs.
3D integration has yet to be adopted by mainstream chip-makers as the main focus
currently is on shrinking chip size and the performance/power consumption gain
from 3D integration is less than that from chip shrinking/FinFET. We believe the
mainstream chip-makers are likely to start working on 3D pilot lines while
continuing to shrink chips. In our model, we have included one shipment each for
2014 and 2015. Our bull-case scenario assumes all mainstream IDMs, memory and
packaging houses will start building their pilot lines in 2014/2015. Excluding the
chip-makers already working with EV Group (Intel and Micron, we believe), the
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