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ETC273232K BIT (4K x 8) CMOS UV ERASABLE PROM• CMOS POWER CONSUMPTION: 26.25 mWMAX ACTIVE POWER, 0.53 mW MAXSTANDBY POWER• 4096 x 80RGANIZZATION• PIN COMPATIBLE TO M/ET2716, ETC2716,M2732A,• ACCESS TIME DOWN TO 350 ns• SINGLE 5V POWER SUPPLY• STATIC - NO CLOCKS REQUIRED• TTL COMPATIBLE II0s DURING BOTH READAND PROGRAM MODES• THREE-STATE OUTPUT WITH OR-TIECAPABILITY• OPER. TEMP. : 0 to + 70°C; - 40 to + 85°C(V suffix).QDIP-24(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe ETC2732 is a high speed 32K UV erasable andelectrically reprogrammable CMOS EPROM, ideallysuited for applications where fast turn-around,pattern experimentation and low power consumptionare important requirements.The ETC2732 is packaged in a 24-pin dual-in-linepackage with transparent lid. The transparent lidallows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then bewritten into the device by following the programmingprocedure.This EPROM is fabricated with thereliable, high volume, time proven, p2 CMOS silicongate technology.PIN NAMESAO-A11ADDRESS INPUTS0 0-0 7 DATA OUTPUTSCEOEVppVeeVssCHIP ENABLEOUTPUT ENABLEREAD RV, PROGRAM 25V5VGROUNDA7A6ASA4A3A2A1AO000102vssveeASA9A11OEIVPPJune 19881/10101
ETC2732BLOCK DIAGRAMVCC~5VGNDl\ISS)~GNDOE/C~EPP -tl_......:CO---.NT_R_O_L_j___:·11--l LOGICiYDECODERDATA OUTPUTS00-0 7OUTPUT BUFFERSY. GATINGAD-<strong>Al</strong>l~DDRESSINPUTSXDECODER32,768-BITCELL MATRIX---+L-________ r---~ ________ ~PIN CONNECTION DURING READ OR PROGRAMMODEPIN NAME/NUMBERCE OE/Vpp Vee18 20 24READ VIL VIL 5VSTANDBY VIH Don't Care 5VPROGRAM VIL 25V 5VPROGRAM VERIFY VIL VIL 5VPROGRAM INHIBIT VIH 25V 5V• Symbol in parentheses are proposed JEDEC standard.OUTPUTS9-11,13-17DOUTHi-ZDINDOUTHi-ZABSOLUTE MAXIMUM RATINGSSymbol Parameter ValueTamb Temperature Under Bias -10to +80I'V" range -50 to +95Tstg Storage Temperature -65 to +125Vpp Vpp Supply Voltage with Respect to VSS 26.5V to - 0.3Yin Input Voltages with Respect to VSS except VPP 6V to -0.3Output Voltages with Respects to VSSVCC+0.3V toVSS~0:3VPo Power Dissipation 1.0WLead Temperature (Soldering 10 seconds)300 ......°CNote 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "OperatingTemperature Range" they are, not meant to imply that the devices should be operated at the~e limijs. The table of "Electric.alCharacteristics" provides conditions for actual device operation. . -Unit°C°C°CVV2/10102
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MEMORY PRODUCTSDATABOOK1st EDITIONJ
Page 4:
TABLE OF CONTENTSGENERAL INDEX Page
Page 7 and 8:
GENERAL INDEXPageROM DEVICES ......
Page 10 and 11:
GENERAL INFORMATIONThe SGS-THOMSON
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SELECTION GUIDECMOS UV EPROMPart Nu
Page 14 and 15:
SELECTION GUIDECMOS OTP ROMPart Num
Page 16 and 17:
SELECTION GUIDEZEROPOWERPart Number
Page 18 and 19:
SELECTION GUIDEFAST STATIC RAMPart
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12 32Kx8 NMOS M27256FUV EPROMPRODUC
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VFSRAMPRODUCTDESCRIPTIONSGS-THOMSON
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EPROM DEVICESNMOS UV EPROM23
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ET2716/M2716BLOCK DIAGRAM~ VPP'5V+-
Page 29 and 30:
ET2716/M2716AC TEST CONDITIONSOutpu
Page 31 and 32:
ET2716/M2716ERASINGThe M/ET2716 is
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ET2716/M2716SWITCHING TIME WAVEFORM
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M2732A32K (4K x 8) NMOS UV ERASABLE
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M2732AREAD OPERATIONDC AND AC CONDI
Page 40 and 41:
M2732APROGRAMMING OPERATION(l) (T a
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M2732APROGRAMMING OPERATION (Contin
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M2764ABLOCK DIAGRAMDATA OUTPUT00- 0
Page 47 and 48:
M2764AREAD OPERATION (Continued)AC
Page 49 and 50:
M2764ADEVICE OPERATION (Continued)T
Page 51 and 52: M2764APROGRAMMING WAVEFORMSV1HADDRE
Page 53 and 54: M2764AORDERING INFORMATIONPart Numb
Page 55 and 56: M27128ABLOCK DIAGRAMVceO--GND o--
Page 57 and 58: M27128AREAD OPERATION (Continued)AC
Page 59 and 60: M27128ADEVICE OPERATION (Continued)
Page 61 and 62: M27128APROGRAMMING WAVEFORMSIVIHADD
Page 63 and 64: M27128AORDI:RING INFORMATIONPart Nu
Page 65 and 66: M27256BLOCK DIAGRAMVeco----GNOo-
Page 67 and 68: M27256READ OPERATION (Continued)AC
Page 69 and 70: M27256DEVICE OPERATION (Continued)P
Page 71 and 72: M27256PROGRAMMING WAVEFORMSPROGRAMP
Page 73 and 74: M27256ORDERING INFORMATIONPart Numb
Page 75 and 76: M27512BLOCK DIAGRAMVee o-----?GNOO-
Page 77 and 78: M27512AC TEST CONDITIONSOutput Load
Page 79 and 80: M27512DEVICE OPERATIONS (Continued)
Page 81 and 82: M27512DEVICE OPERATION (Continued)M
Page 83 and 84: M27512PROGRAMMING OPERATION (T amb=
Page 85 and 86: M27512M27512 DESIGN INNOVATIONS FOR
Page 87 and 88: M27512Figure 7 - M27512 Sensing sch
Page 90: EPROM DEVICESCMOS UV EPROM89
Page 93 and 94: ETC2716BLOCK DIAG~AM+-- vpp+-- vcc+
Page 95 and 96: ETC2716AC TEST CONDITIONSOutput Loa
Page 97 and 98: ETC2716ERASING~he ETC?716 !s erased
Page 99 and 100: ETC2716SWITCHING TIME WAVEFORMSR.ed
Page 104 and 105: ETC2732READ OPERATIONDC CHARACTERIS
Page 106 and 107: ETC2732DEVICE OPERATIONThe five mod
Page 108 and 109: ETC2732PROGRAMMING WAVEFOR'''SNote:
Page 110 and 111: ETC2732SWITCHING TIME WAVEFORMSRead
Page 112 and 113: TS27C64AQ64K (8K x 8) CMOS UV ERASA
Page 114 and 115: TS27C64AQREAD OPERATIONDC CHARACTER
Page 116 and 117: TS27C64AQDEVICE OPERATIONThe seven
Page 118 and 119: TS27C64AQAC TEST CONDITIONSInput ri
Page 120: TS27C64AQORDERING INFORMATIONPart N
Page 123 and 124: TS27C256QBLOCK DIAGRAMVee 0----.GND
Page 125 and 126: TS27C256QAC TEST CONDITIONSOutput L
Page 127 and 128: TS27C256QERASINGThe TS27C256 is era
Page 129 and 130: TS27C256QHIGH SPEED PROGRAMMING FLO
Page 131 and 132: ,1,;'"
Page 133 and 134: ST27C1001BLOCK DIAGRAMv P P cr-----
Page 135 and 136: M27C1024BLOCK DIAGRAMVpp 0----:---+
Page 137 and 138: M27C1024AC TEST CONDITIONSOutput Lo
Page 139 and 140: M27C,1024PROGRAM INHIBITProgramming
Page 141 and 142: M27C1024PROGRAMMING WAVEFORMSVIHADD
Page 143 and 144: M27C1024ORDERING INFORMATIONPart Nu
Page 146 and 147: ST2764AP64K (8K x 8) NMOS ONE TIME
Page 148 and 149: ST2764APREAD OPERA nONDC AND AC CON
Page 150 and 151: ST2764APDEVICE OPERATIONThe seven m
Page 152 and 153:
ST2764APPROGRAMMING OPERATION (Tamb
Page 154 and 155:
ST2764APFAST PROGRAMMING FLOWCHART9
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ST27128AP128K (16K x 8) NMOS ONE TI
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ST27128APREAD OPERATIONDC AND AC CO
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ST27128APDEVICE OPERATIONThe seven
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ST27128APPROGRAMMING OPERATION (Tam
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ST27128APFAST PROGRAMMING FLOWCHART
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ST27256P256K (32K x 8) NMOS ONE TIM
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ST27256PREAD OPERATIONDC AND AC CON
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ST27256PDEVICE OPERATIONThe eight m
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ST27256PPROGRAMMING OPERATION (Tamb
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ST27256PFAST PROGRAMMING FLOWCHARTF
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EPROM DEVICESCMOS OTP ROM175
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TS27C64AFN-TS27C64APBLOCK DIAGRAMVe
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TS27C64AFN-TS27C64APAC TEST CONDITI
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TS27C64FN-TS27C64APPROGRAMMINGOPERA
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TS27C64AFN-TS27C64APHIGH SPEED PROG
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TS27C64AFN~TS27C64APORDERING INFORM
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ST27C256FN-ST27C256PBLOCK DIAGRAMVc
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ST27C256FN·ST27C256PAC TEST CONDIT
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ST27C256FN-ST27C256PPROGRAMMING CHA
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ST27C256FN·ST27C256PHIGH SPEED PRO
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ST27C256FN-ST27C256PORDERING INFORM
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SGS-1HOMSON~ ., L ~D©ffi1@rn[brn©
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M8571ELECTRICAL CHARACTERISTICS (0
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M8571S-BUS DESCRIPTION (Continued)A
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M8571S·BUS INTERFACEThe serial, 3-
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M8571MASTER. READS AFTER SETTING WO
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M8571ORDERING INFORMATIONPort Numbe
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M9306BLOCK DIAGRAM00DI---+-+-+-+---
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M93D6FUNCTIONAL DESCRIPTIONThe inpu
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M9306ORDERING INFORMATIONPart Numbe
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M9346BLOCK DIAGRAMDl~-r------------
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M9346FUNCTIONAL DESCRIPTIONThe inpu
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M9346INSTRUCTION SETInstruction S8
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M9346TIMING DIAGRAMS (Continued)INS
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EEPROM DEVICESCMOS EEPROM227
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ST24C02BLOCK DIAGRAMseL--~~--~-----
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ST24C02FIG. 2A· DATA TRANSFER SEQU
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ST24C02ELECTRICAL CHARACTERISTICSAC
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ST24C02FIG. 4A· PAGE WRITEBUS ACTI
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TS59C111 K BIT SERIAL CMOS EEPROM
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TS59C11READ OPERATIONDC CHARACTERIS
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TS59C11The READ instruction is the
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TS59C11FIG. 5b - ERAL (Erase all) M
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~ SGS-1HOMSONIt.. ~ L [j\I'A]O©OO@
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TS93C46READ OPERATIONDC CHARACTERIS
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TS93C46INSTRUCTION TIMINGSREADSK ~u
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~TS93C46ORDERING INFORMATIONPart Nu
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ST93C56BLOCK DIAGRAMPROTECTREGISTER
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M2316H16K-BIT READ ONLY MEMORY• S
Page 262 and 263:
M2316HSTATIC ELECTRICAL CHARACTERIS
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M2332M233332K-BIT READ ONLY MEMORY
Page 266 and 267:
M2332/M2333DC AND OPERATING CHARACT
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~ SGS-11I0MSONA., L ~D©[Ri@~[lJ~©
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M2364DC AND OPERATING CHARACTERISTI
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M236564K-BIT READ ONLY MEMORY• PI
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M2365DC AND OPERATING CHARACTERISTI
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STATIC RAM DEVICES275
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MK48Z02N2(B)-12115/20/25DESCRIPTION
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MK48Z02112(B)-12115/20/25WRITE MODE
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MK48Z02/12(B)-12/15/20/25FIGURE 6.
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MK48Z02/12(B)-12/15/20/25FIGURE 7.
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MK48Z02112(B}-12115/20/25AC TEST CO
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MK48C02A/12A(K, N)·15/20/252K x 8
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MK48C02AI12A(K,N)-15/20/25OPERATION
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MK48C02A/12A(K, N)-15/20/25DATA RET
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MK48C02A112A(K,N)-15/20/25FIGURE 6.
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MK48C02A112A(K,N)-15/20/25AC TEST C
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MK48T02/12(B)-12/15120/252K x 8 ZER
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MK48T02/12(B)-12/15/20/25OPERATIONR
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MK48T02N 2(8)-12/15/20/25CLOCK OPER
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MK48T02112(B)-12/15/20/25The FT bit
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MK48T02112(B)-12115/20/25PREDICTING
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MK48T02112(B)-12/15/20/25~redlctlng
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MK48TD2/12(B)-12115/20/25ABSOWTE MA
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M K48Z08/18/09/19(B)·15/201258K x
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MK48Z08/18/09/19(B)-15/20/25OPERATI
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MK48Z08118/09/19(B)-15/20/25AC ELEC
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MK48Z08118/09119(B)-15/20/25DATA RE
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MK48Z08118/09119(B)-15/20/25ABSOWTE
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MK48Z08/18/09/19(B)-15/20/25PACKAGE
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MKI48Z02112(B)-15/20/25DESCRIPTIONT
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M KI48Z02112(B)-15/20J25WRITE MODET
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MKI48Z02/12(B.)-15/20/25FIGURE.6. P
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MKI48Z02/12(B)-15/20/25FIGURE 7. MK
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MKI48Z02112(B)-1S/20/2SAC TEST COND
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~ SGS-THOMSON..""! L ~o©oo@rn[!J~
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MK48T08 (8)-10/12/15/20READ MODEThe
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MK48T08 (8)-10/12/15/20AC ELECTRICA
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MK48T08 (8)-10/12/15/20CLOCK OPERAT
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MK48T08 (B)-10112/15/20FIGURE 8. FR
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MK48T08 (8)-10/12/15/20rhe t 10/0 f
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MK48T08 (8)-10/12/15/20PACKAGE DESC
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STATIC RAM DEVICESCACHE TAG RAM353
Page 357 and 358:
MK41 HSO(N, P)-20/25/35FIGURE 2. CO
Page 359 and 360:
MK41H80(N,P)-20/25/35APPLICATIONThe
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MK41H80(N,P)-20/25/35ABSOWTE MAXIMU
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MK41 H80(N ,P)-20/25/35NORMALIZED D
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MK41H8O(N,P),-2OI2513522 PIN "P" PA
Page 367 and 368:
MK4202(Q)-20TRUTH TABLERS S E WHi -
Page 369 and 370:
MK4202(Q)-20DEVICE DESCRIPTION AND
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MK4202(Q)-20READ MODEThe MK4202 is
Page 373 and 374:
MK4202(Q)-20COMPARE CYCLE TIMINGEle
Page 375 and 376:
MK4202(Q)-20FIGURE 5. W WRITE CYCLE
Page 377 and 378:
MK4202(Q)-20FIGURE 10. CHIP SELECT
Page 379 and 380:
MK4202(Q)-20FIGURE 15. LATE WRITE·
Page 381 and 382:
MK4202(Q)-20FIGURE 21. RESET CYCLEr
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MK4202(Q)-20AC TEST CONDITIONSInput
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MK48H74(N,P,E)·35/45/55DESCRIPTION
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MK48H74(N,P,E)-35/45/55WRITE MODETh
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MK48H74(N, P, E)-35/45/S5COMPARE MO
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MK48H74(N,P,E)-35/45/55APPLICATIONT
Page 393 and 394:
MK48H74(N,P,E)-35/45/55AC TEST COND
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STATIC RAM DEVICESFIFO395
Page 399 and 400:
MK4501(N,K)-65/80/10112115/20a rate
Page 401 and 402:
MK4501 (N, K)-65/80/1 0112/15/20REA
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MK4501 (N, K)-65/80/10/12/15/20RESE
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M K4501(N, K)-65/80110/12115/20SING
Page 407 and 408:
MK4501(N,K)-65/80110112/15/20EXPANS
Page 409 and 410:
MK4501(N, K)-65/80110/12/15/20COMPO
Page 411 and 412:
MK4501 (N, K)-65/80110112115/20FIGU
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~ SGS-1HOMSON,."'! I. ~u©oo@rn[brn
Page 416 and 417:
MK4503(N,K)-50/65/80/10/12/15/20WRI
Page 418 and 419:
MK4S03(N ,K)-SO/6S/80/1 0/12/1S/20F
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MK4503(N ,K)-50/65/80110112/15/20RE
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MK4S03(N, K)-S0/6S/80110112/1S/20HA
Page 424 and 425:
MK4S03(N ,K)-SO/6S/80110112I1S/20EX
Page 426 and 427:
MK4503(N, K)-50/65/80/10112/15/20CO
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MK4S03(N, K)-SO/6S/80/1 0/1211 S/20
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MK4511(N,K)-12/15/20512 x 8 CMOS Bi
Page 432 and 433:
MK4511(N,K)-12115/20READ MODEThe MK
Page 434 and 435:
MK4511(N,K)-12115/20DUAL PORT OPERA
Page 436 and 437:
MK4511 (N,K)-12115/20IMPLEMENTATION
Page 438 and 439:
MK4511(N,K)-12/15/20ABSOWTE MAXIMUM
Page 440:
MK4511(N,K)-12115/20FIGURE 11. MK45
Page 443 and 444:
M K4505M/4505S(N)-25/33/50DESCRIPTI
Page 445 and 446:
MK4505M/4505S(N)-25/33/50AC ELECTRI
Page 447 and 448:
MK4505M/4505S(N)-25/33/50FIGURE S.
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M K4505M/4505S(N)-25/33/50FIGURE 9.
Page 451 and 452:
MK4505M/4505S(N)-25/33/50SIMULTANEO
Page 453 and 454:
MK4505M/4505S{N)-25/33/50FIGURE 13.
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MK4505M/4505S(N)-25/33/50ABSOWTE MA
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MK4S0SM/4S0SS(N)-2S/33/S020 PIN uN"
Page 459 and 460:
MK4S264/4S26S(N)-SS/70FIGURE 2. DEV
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MK45264/45265(N)-55nOAC ELECTRICAL
Page 463 and 464:
MK45264/45265(N)-55noReadlWriteThe
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MK45264/45265(N)-55noFIGURE 8. FULL
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MK4S264/4S26S(N)-SSnoFIGURE 13. TRA
Page 469 and 470:
MK45264/45265(N)-55noFIGURE 18. WRI
Page 471 and 472:
MK4S264/4S26S(N)-SSI7OAC TEST CONDI
Page 473 and 474:
MK45264/45265(~)-5snoWidth Expansio
Page 475 and 476:
MK45264/45265(N)-55noORDERING INFOR
Page 478 and 479:
MK41H661M K41 H67(N, P)-20/25/3516K
Page 480 and 481:
MK41H66/MK41 H67(N, P)-20/25/35WRIT
Page 482 and 483:
MK41H66/MK41H67(N,P)-20/25135APPLIC
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MK41H66/MK41H67{N,P)-20/25/35NORMAL
Page 486 and 487:
MK41 H66/MK41 H67(N ,P)-20/25/35ORD
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MK41H681MK41H69(N,P)-20/25/354K x 4
Page 490 and 491:
MK41 H68/MK41 H69(N, P)-20/25/35WRI
Page 492 and 493:
MK41H68/MK41 H69(N ,P)-20/25/35APPL
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MK41 H68/MK41 H69(N ,P)-20/25/35NOR
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MK41H68/MK41H69(N,P)-20/25/35ORDERI
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t==' SGS-1HOMSON. ..,1. ~o©oo@rn[]
Page 500 and 501:
MK41 H79(N,P)·20125/35WRITE MODETh
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MK41 H79(N, P)-20/25/35ITANDBY MODE
Page 504 and 505:
MK41 H79(N ,P)-20/25/35"C TEST COND
Page 506 and 507:
MK41H79(N,P)-20/25/35~ORMALIZED DC
Page 508 and 509:
MK41 H87(N)-25/35/4564K x 1 CMOS ST
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MK41H87(N)-25/35/45WRITE MODEThe MK
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MK41H87(N)-25/35/45STANDBY MODEThe
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MK41 H87(N)-25/35/45AC TEST CONDITI
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.35, 45, 55, AND 70 ns ADDRESS ACCE
Page 518 and 519:
MK48H64/MK48H65(N,P)-35/45/55noREAD
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MK48H64/MK48H65(N,P)-35/45/55noWRIT
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MK48H64/MK48H65(N,P)-35/45/55noABSO
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SALES OFFICESAUSTRALIANSW 2027 EDGE
Page 527:
Information furnished is believed t
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