memory products - Al Kossow's Bitsavers

M85715) WORD ADDRESS/OPCODEThe second byte transmitted in a write sequencecan assume several meaning according to thevalue of the MS pin. In any case, it carries all theinformations the M8571 needs to perform thedesired operation.MS can assume three different values:- VIL (VIN :$ 1.5V)- VIH (3.0V :$ VIN < Vce + 1)- VH (9.0V :$ VIN :$ 12V)With regards to the value of MS, the possible behavioursare:a) MS = VIL ("RAM mode")In this mode the M8571 is compatible with thePCD 8571 RAM (128 x 8bit). The second byteof the sequence gives the address of the wordto be selected, both for write and for read:1. xyyyyyyy Ayyyyyyy is the word address; the first bitis "don't care; the main feature of thismode are the following:the memory appears as an 128 x 8 arrayonly "byte operations are allowed;EIW operations are stopped by thefollowing accesses.b) MS = VIH (EEPROM mode)The word address-byte now must be regarded asmixed address-opcode byte; more precisely, thefirst three bits indicate the meaning to be attributedto the remainder of the byte. The possible combinationsare:Oyyyyyyy10yyyyyy110yyyyy11111111111000001110010011110001byte-mode (8 bits) RD or EIWat address yyyyyyyword-mode (16 bits) RD or EIWat address yyyyyypage-mode (32 bits) RD or EIWat address yyyyyEIW cycle stopRead busy bitBlock Erase (needs VH on MSpin, see also BLOCK mode)Reload Address Register withpre-increment dataIn this mode, as well as in RAM mode, the "busy"information is transmitted from the M8571 to themaster using the "no acknowledge" format. Furthermore,"Read busy bit" instruction, which is alwaysanswered by the M8571 no matter what it isdoing, allows the master to know wheter the "noacknowledge" condition comes from a "busy" statusor from a malfunction; the "busy" status is signalledby the byte 11100101; the "no busy" by00011010.Also in this mode the self-incrementing addressregister is available, both for read and for write, foreach word length.The M8571 is provided with a double register forstoring the address that is sent during the secondbyte of a write sequence.When the self-incrementing is used, this addressbecomes the "starting address" of the modifiedstring of bytes. The "reload" instruction allows themaster to recover this address if it wants to readthe modified string from the beginning, without theneed for external storage of the "starting address".c) MS = VH (BLOCK mode)The only instruction that can be executed in thismode is "Block Erase", which is useful to erasethe whole array in a single shot. This can occureither during testing or at the set-up of a new system,when the whole memory must be written.When this instruction is given, the self-timing circuitryis disabled, so that the operation must bestopped (after tBE) by the master executing aSTART on the bus. The "enable" feature obtainedwith the non standard level on MS was added toavoid unintentional clearing of the whole memory,whenever the "Block Erase" code was erroneouslysent.6) 16-bit or 32-bit OPERATIONSThe obvious advantage of an operation on 16 bits(a word) or on 32 bits (a page) is that the EIW timeis 1 Oms for the whole word or page. When a wordor page mode operation is required, the device behaviourundergoes some slight modifications:The M8571 waits for receiving all the bytes thatcompose the word or the page before starting anEIW operation;- The self-incrementing address register keeps intoaccount the word or page lenght so that, at theend of a word or page mode operation, it pOintsto the next word or page.10/11208