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MK4511 (N,K)-12115/20IMPLEMENTATIONUse of the interrupt feature is completely optional,allowing simple implementation of either interruptdriven or polled inter-processor communications applications.Either port can read or write any of the512 bytes without restriction. Users who choose notto utilize the interrupt feature should leave the interruptpins unconnected.Any inter-processor communications application willdoubtless employ sorge ~pe of sem~hore scheme.The use of the REOI A ,ENNDiS and ACKIRDYbits allow for each port to follow the exact statusof the other port. The following example covers thecase of port X interrupting port Y but applies equallywell for port Y interrupting port X.An Example Approach to Inter-processor CommunicationsUsing Pre-Allocated Memory Blocksand InterruptsPre-define six memory blocks of 85 bytes each (fora total of 510 bytes). Assign some number of blocks(probably three) to the X port and the balance tothe Y port. Each port will write only to its assignedmemory blocks, preventing port X and port Y attemptingto load their messages into the same area.Write the message to be passed into the Port X messagearea. When finished, read ACKlRDYy . Ifready, request an interrupt on port Y by writing a1 into REO/CANx. Indicate which messageblock(s) contain valid message data, using the uppersix bits of the interrupt register byte.Now, acknowledge the interrupt to Port Y by writinga 1 to the acknowledge flag on Port Y. Beginreading the message via Port Y. The acknowledgeshould not be removed until after the message Basbeen read. When it has been, set the ACKIR ¥yflag to ready.ports attempting to write at the same address or oneport reading and one writing at the same addressat the same time.While a collision is generally considered undesirable,the conditions that can lead to iII-defined resultsare definable and manageable. In the case of awritelwrite collision, the data stored at the addressin question mayor may not have any similarity toeither write attempted or the previously residentdata if the delay between the ends of the writes(twwJis not long enough. On the other hand,write/read collisions do not affect the integrity of datastorage, but do have an impact on the validity ofoutput data at definable pOints in time (1001 andIoov). Figures 7 and 8 describe these conditions.All of the parameters indicated reference the validityof the entire byte of data. Individual bits of a bytechange state at slightly different rates. Though thisis a subtle distinction, it is nonetheless important,particularly in the case of monitoring ACKIRDY. Beaware that a read may catch the ready bit at a validzero before the rest of the byte has finished transition.Nevertheless, because there is no reason forthe ready bit to go low, other than that the oppositeport is writing a zero into it, catching it low isa reliable indication that the other port is ready. Thisis all to say that single significant bit flag write/readoperations can proceed reliably under collision conditionswhere byte wide operations cannot.Simultaneous reads at the same address will alwaysproduce valid data and are therefore not considereda collision in this context.FIGURE 7. MINIMUM WRITE TO WRITE LATENCYFOR VALID DATA STORAGE"".Check to see that the message was received. MonitorACKlRDYy via Port X. Changes to the messageblock should not be made by Port X untilACKlRDYy is zero, indicating Port Y has finishedreading its message.COLLISIONThe central objective of the MK4511 design effortwas to produce a component that makes implementationof asynchronous, random access dual portmemory applications, that can assure data integrity,as simple and inexpensive to design and implementas possible.Data Integrity can be called into question if port toport collision occurs. A collision is defined as both\ /7111435
MK4511(N,K)-12115/20FIGURE 8. SIMULTANEOUS READ WRITE TIMINGCE x\/WEx1ADxIODYADyVALID DATA OUTNEW VALID DATA OUTOEy'"IICEA~10EZtCEZIbCEyCOLLISION TIMINGAC ELECTRICAL CHARACTERISTICS(O°C:sT A:s70°C) (Vee = 5.0 V ± 10 percent)MK4511-12MK4511-15MK4511-20SYM PARAMETERS MIN MAXtoOl Output Data Indeterminant 10tODV Output Data Valid 90tWWL Write to Write Latency 80MIN MAX MIN MAX UNITS NOTES10 10 ns115 150 ns105 130 ns8/11436
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MEMORY PRODUCTSDATABOOK1st EDITIONJ
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TABLE OF CONTENTSGENERAL INDEX Page
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GENERAL INDEXPageROM DEVICES ......
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GENERAL INFORMATIONThe SGS-THOMSON
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SELECTION GUIDECMOS UV EPROMPart Nu
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SELECTION GUIDECMOS OTP ROMPart Num
Page 16 and 17:
SELECTION GUIDEZEROPOWERPart Number
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SELECTION GUIDEFAST STATIC RAMPart
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12 32Kx8 NMOS M27256FUV EPROMPRODUC
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VFSRAMPRODUCTDESCRIPTIONSGS-THOMSON
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EPROM DEVICESNMOS UV EPROM23
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ET2716/M2716BLOCK DIAGRAM~ VPP'5V+-
Page 29 and 30:
ET2716/M2716AC TEST CONDITIONSOutpu
Page 31 and 32:
ET2716/M2716ERASINGThe M/ET2716 is
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ET2716/M2716SWITCHING TIME WAVEFORM
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M2732A32K (4K x 8) NMOS UV ERASABLE
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M2732AREAD OPERATIONDC AND AC CONDI
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M2732APROGRAMMING OPERATION(l) (T a
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M2732APROGRAMMING OPERATION (Contin
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M2764ABLOCK DIAGRAMDATA OUTPUT00- 0
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M2764AREAD OPERATION (Continued)AC
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M2764ADEVICE OPERATION (Continued)T
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M2764APROGRAMMING WAVEFORMSV1HADDRE
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M2764AORDERING INFORMATIONPart Numb
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M27128ABLOCK DIAGRAMVceO--GND o--
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M27128AREAD OPERATION (Continued)AC
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M27128ADEVICE OPERATION (Continued)
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M27128APROGRAMMING WAVEFORMSIVIHADD
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M27128AORDI:RING INFORMATIONPart Nu
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M27256BLOCK DIAGRAMVeco----GNOo-
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M27256READ OPERATION (Continued)AC
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M27256DEVICE OPERATION (Continued)P
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M27256PROGRAMMING WAVEFORMSPROGRAMP
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M27256ORDERING INFORMATIONPart Numb
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M27512BLOCK DIAGRAMVee o-----?GNOO-
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M27512AC TEST CONDITIONSOutput Load
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M27512DEVICE OPERATIONS (Continued)
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M27512DEVICE OPERATION (Continued)M
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M27512PROGRAMMING OPERATION (T amb=
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M27512M27512 DESIGN INNOVATIONS FOR
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M27512Figure 7 - M27512 Sensing sch
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EPROM DEVICESCMOS UV EPROM89
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ETC2716BLOCK DIAG~AM+-- vpp+-- vcc+
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ETC2716AC TEST CONDITIONSOutput Loa
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ETC2716ERASING~he ETC?716 !s erased
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ETC2716SWITCHING TIME WAVEFORMSR.ed
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ETC273232K BIT (4K x 8) CMOS UV ERA
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ETC2732READ OPERATIONDC CHARACTERIS
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ETC2732DEVICE OPERATIONThe five mod
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ETC2732PROGRAMMING WAVEFOR'''SNote:
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ETC2732SWITCHING TIME WAVEFORMSRead
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TS27C64AQ64K (8K x 8) CMOS UV ERASA
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TS27C64AQREAD OPERATIONDC CHARACTER
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TS27C64AQDEVICE OPERATIONThe seven
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TS27C64AQAC TEST CONDITIONSInput ri
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TS27C64AQORDERING INFORMATIONPart N
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TS27C256QBLOCK DIAGRAMVee 0----.GND
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TS27C256QAC TEST CONDITIONSOutput L
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TS27C256QERASINGThe TS27C256 is era
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TS27C256QHIGH SPEED PROGRAMMING FLO
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,1,;'"
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ST27C1001BLOCK DIAGRAMv P P cr-----
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M27C1024BLOCK DIAGRAMVpp 0----:---+
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M27C1024AC TEST CONDITIONSOutput Lo
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M27C,1024PROGRAM INHIBITProgramming
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M27C1024PROGRAMMING WAVEFORMSVIHADD
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M27C1024ORDERING INFORMATIONPart Nu
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ST2764AP64K (8K x 8) NMOS ONE TIME
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ST2764APREAD OPERA nONDC AND AC CON
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ST2764APDEVICE OPERATIONThe seven m
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ST2764APPROGRAMMING OPERATION (Tamb
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ST2764APFAST PROGRAMMING FLOWCHART9
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ST27128AP128K (16K x 8) NMOS ONE TI
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ST27128APREAD OPERATIONDC AND AC CO
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ST27128APDEVICE OPERATIONThe seven
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ST27128APPROGRAMMING OPERATION (Tam
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ST27128APFAST PROGRAMMING FLOWCHART
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ST27256P256K (32K x 8) NMOS ONE TIM
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ST27256PREAD OPERATIONDC AND AC CON
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ST27256PDEVICE OPERATIONThe eight m
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ST27256PPROGRAMMING OPERATION (Tamb
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ST27256PFAST PROGRAMMING FLOWCHARTF
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EPROM DEVICESCMOS OTP ROM175
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TS27C64AFN-TS27C64APBLOCK DIAGRAMVe
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TS27C64AFN-TS27C64APAC TEST CONDITI
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TS27C64FN-TS27C64APPROGRAMMINGOPERA
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TS27C64AFN-TS27C64APHIGH SPEED PROG
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TS27C64AFN~TS27C64APORDERING INFORM
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ST27C256FN-ST27C256PBLOCK DIAGRAMVc
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ST27C256FN·ST27C256PAC TEST CONDIT
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ST27C256FN-ST27C256PPROGRAMMING CHA
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ST27C256FN·ST27C256PHIGH SPEED PRO
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ST27C256FN-ST27C256PORDERING INFORM
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SGS-1HOMSON~ ., L ~D©ffi1@rn[brn©
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M8571ELECTRICAL CHARACTERISTICS (0
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M8571S-BUS DESCRIPTION (Continued)A
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M8571S·BUS INTERFACEThe serial, 3-
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M8571MASTER. READS AFTER SETTING WO
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M8571ORDERING INFORMATIONPort Numbe
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M9306BLOCK DIAGRAM00DI---+-+-+-+---
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M93D6FUNCTIONAL DESCRIPTIONThe inpu
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M9306ORDERING INFORMATIONPart Numbe
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M9346BLOCK DIAGRAMDl~-r------------
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M9346FUNCTIONAL DESCRIPTIONThe inpu
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M9346INSTRUCTION SETInstruction S8
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M9346TIMING DIAGRAMS (Continued)INS
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EEPROM DEVICESCMOS EEPROM227
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ST24C02BLOCK DIAGRAMseL--~~--~-----
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ST24C02FIG. 2A· DATA TRANSFER SEQU
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ST24C02ELECTRICAL CHARACTERISTICSAC
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ST24C02FIG. 4A· PAGE WRITEBUS ACTI
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TS59C111 K BIT SERIAL CMOS EEPROM
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TS59C11READ OPERATIONDC CHARACTERIS
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TS59C11The READ instruction is the
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TS59C11FIG. 5b - ERAL (Erase all) M
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~ SGS-1HOMSONIt.. ~ L [j\I'A]O©OO@
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TS93C46READ OPERATIONDC CHARACTERIS
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TS93C46INSTRUCTION TIMINGSREADSK ~u
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~TS93C46ORDERING INFORMATIONPart Nu
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ST93C56BLOCK DIAGRAMPROTECTREGISTER
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M2316H16K-BIT READ ONLY MEMORY• S
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M2316HSTATIC ELECTRICAL CHARACTERIS
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M2332M233332K-BIT READ ONLY MEMORY
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M2332/M2333DC AND OPERATING CHARACT
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~ SGS-11I0MSONA., L ~D©[Ri@~[lJ~©
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M2364DC AND OPERATING CHARACTERISTI
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M236564K-BIT READ ONLY MEMORY• PI
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M2365DC AND OPERATING CHARACTERISTI
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STATIC RAM DEVICES275
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MK48Z02N2(B)-12115/20/25DESCRIPTION
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MK48Z02112(B)-12115/20/25WRITE MODE
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MK48Z02/12(B)-12/15/20/25FIGURE 6.
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MK48Z02/12(B)-12/15/20/25FIGURE 7.
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MK48Z02112(B}-12115/20/25AC TEST CO
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MK48C02A/12A(K, N)·15/20/252K x 8
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MK48C02AI12A(K,N)-15/20/25OPERATION
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MK48C02A/12A(K, N)-15/20/25DATA RET
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MK48C02A112A(K,N)-15/20/25FIGURE 6.
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MK48C02A112A(K,N)-15/20/25AC TEST C
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MK48T02/12(B)-12/15120/252K x 8 ZER
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MK48T02/12(B)-12/15/20/25OPERATIONR
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MK48T02N 2(8)-12/15/20/25CLOCK OPER
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MK48T02112(B)-12/15/20/25The FT bit
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MK48T02112(B)-12115/20/25PREDICTING
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MK48T02112(B)-12/15/20/25~redlctlng
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MK48TD2/12(B)-12115/20/25ABSOWTE MA
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M K48Z08/18/09/19(B)·15/201258K x
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MK48Z08/18/09/19(B)-15/20/25OPERATI
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MK48Z08118/09/19(B)-15/20/25AC ELEC
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MK48Z08118/09119(B)-15/20/25DATA RE
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MK48Z08118/09119(B)-15/20/25ABSOWTE
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MK48Z08/18/09/19(B)-15/20/25PACKAGE
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MKI48Z02112(B)-15/20/25DESCRIPTIONT
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M KI48Z02112(B)-15/20J25WRITE MODET
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MKI48Z02/12(B.)-15/20/25FIGURE.6. P
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MKI48Z02/12(B)-15/20/25FIGURE 7. MK
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MKI48Z02112(B)-1S/20/2SAC TEST COND
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~ SGS-THOMSON..""! L ~o©oo@rn[!J~
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MK48T08 (8)-10/12/15/20READ MODEThe
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MK48T08 (8)-10/12/15/20AC ELECTRICA
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MK48T08 (8)-10/12/15/20CLOCK OPERAT
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MK48T08 (B)-10112/15/20FIGURE 8. FR
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MK48T08 (8)-10/12/15/20rhe t 10/0 f
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MK48T08 (8)-10/12/15/20PACKAGE DESC
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STATIC RAM DEVICESCACHE TAG RAM353
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MK41 HSO(N, P)-20/25/35FIGURE 2. CO
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MK41H80(N,P)-20/25/35APPLICATIONThe
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MK41H80(N,P)-20/25/35ABSOWTE MAXIMU
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MK41 H80(N ,P)-20/25/35NORMALIZED D
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MK41H8O(N,P),-2OI2513522 PIN "P" PA
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MK4202(Q)-20TRUTH TABLERS S E WHi -
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MK4202(Q)-20DEVICE DESCRIPTION AND
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MK4202(Q)-20READ MODEThe MK4202 is
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MK4202(Q)-20COMPARE CYCLE TIMINGEle
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MK4202(Q)-20FIGURE 5. W WRITE CYCLE
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MK4202(Q)-20FIGURE 10. CHIP SELECT
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MK4202(Q)-20FIGURE 15. LATE WRITE·
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MK4202(Q)-20FIGURE 21. RESET CYCLEr
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MK4202(Q)-20AC TEST CONDITIONSInput
Page 385 and 386: MK48H74(N,P,E)·35/45/55DESCRIPTION
Page 387 and 388: MK48H74(N,P,E)-35/45/55WRITE MODETh
Page 389 and 390: MK48H74(N, P, E)-35/45/S5COMPARE MO
Page 391 and 392: MK48H74(N,P,E)-35/45/55APPLICATIONT
Page 393 and 394: MK48H74(N,P,E)-35/45/55AC TEST COND
Page 396: STATIC RAM DEVICESFIFO395
Page 399 and 400: MK4501(N,K)-65/80/10112115/20a rate
Page 401 and 402: MK4501 (N, K)-65/80/1 0112/15/20REA
Page 403 and 404: MK4501 (N, K)-65/80/10/12/15/20RESE
Page 405 and 406: M K4501(N, K)-65/80110/12115/20SING
Page 407 and 408: MK4501(N,K)-65/80110112/15/20EXPANS
Page 409 and 410: MK4501(N, K)-65/80110/12/15/20COMPO
Page 411 and 412: MK4501 (N, K)-65/80110112115/20FIGU
Page 414 and 415: ~ SGS-1HOMSON,."'! I. ~u©oo@rn[brn
Page 416 and 417: MK4503(N,K)-50/65/80/10/12/15/20WRI
Page 418 and 419: MK4S03(N ,K)-SO/6S/80/1 0/12/1S/20F
Page 420 and 421: MK4503(N ,K)-50/65/80110112/15/20RE
Page 422 and 423: MK4S03(N, K)-S0/6S/80110112/1S/20HA
Page 424 and 425: MK4S03(N ,K)-SO/6S/80110112I1S/20EX
Page 426 and 427: MK4503(N, K)-50/65/80/10112/15/20CO
Page 428 and 429: MK4S03(N, K)-SO/6S/80/1 0/1211 S/20
Page 430 and 431: MK4511(N,K)-12/15/20512 x 8 CMOS Bi
Page 432 and 433: MK4511(N,K)-12115/20READ MODEThe MK
Page 434 and 435: MK4511(N,K)-12115/20DUAL PORT OPERA
Page 438 and 439: MK4511(N,K)-12/15/20ABSOWTE MAXIMUM
Page 440: MK4511(N,K)-12115/20FIGURE 11. MK45
Page 443 and 444: M K4505M/4505S(N)-25/33/50DESCRIPTI
Page 445 and 446: MK4505M/4505S(N)-25/33/50AC ELECTRI
Page 447 and 448: MK4505M/4505S(N)-25/33/50FIGURE S.
Page 449 and 450: M K4505M/4505S(N)-25/33/50FIGURE 9.
Page 451 and 452: MK4505M/4505S(N)-25/33/50SIMULTANEO
Page 453 and 454: MK4505M/4505S{N)-25/33/50FIGURE 13.
Page 455 and 456: MK4505M/4505S(N)-25/33/50ABSOWTE MA
Page 457 and 458: MK4S0SM/4S0SS(N)-2S/33/S020 PIN uN"
Page 459 and 460: MK4S264/4S26S(N)-SS/70FIGURE 2. DEV
Page 461 and 462: MK45264/45265(N)-55nOAC ELECTRICAL
Page 463 and 464: MK45264/45265(N)-55noReadlWriteThe
Page 465 and 466: MK45264/45265(N)-55noFIGURE 8. FULL
Page 467 and 468: MK4S264/4S26S(N)-SSnoFIGURE 13. TRA
Page 469 and 470: MK45264/45265(N)-55noFIGURE 18. WRI
Page 471 and 472: MK4S264/4S26S(N)-SSI7OAC TEST CONDI
Page 473 and 474: MK45264/45265(~)-5snoWidth Expansio
Page 475 and 476: MK45264/45265(N)-55noORDERING INFOR
Page 478 and 479: MK41H661M K41 H67(N, P)-20/25/3516K
Page 480 and 481: MK41H66/MK41 H67(N, P)-20/25/35WRIT
Page 482 and 483: MK41H66/MK41H67(N,P)-20/25135APPLIC
Page 484 and 485: MK41H66/MK41H67{N,P)-20/25/35NORMAL
Page 486 and 487:
MK41 H66/MK41 H67(N ,P)-20/25/35ORD
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MK41H681MK41H69(N,P)-20/25/354K x 4
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MK41 H68/MK41 H69(N, P)-20/25/35WRI
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MK41H68/MK41 H69(N ,P)-20/25/35APPL
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MK41 H68/MK41 H69(N ,P)-20/25/35NOR
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MK41H68/MK41H69(N,P)-20/25/35ORDERI
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t==' SGS-1HOMSON. ..,1. ~o©oo@rn[]
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MK41 H79(N,P)·20125/35WRITE MODETh
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MK41 H79(N, P)-20/25/35ITANDBY MODE
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MK41 H79(N ,P)-20/25/35"C TEST COND
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MK41H79(N,P)-20/25/35~ORMALIZED DC
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MK41 H87(N)-25/35/4564K x 1 CMOS ST
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MK41H87(N)-25/35/45WRITE MODEThe MK
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MK41H87(N)-25/35/45STANDBY MODEThe
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MK41 H87(N)-25/35/45AC TEST CONDITI
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.35, 45, 55, AND 70 ns ADDRESS ACCE
Page 518 and 519:
MK48H64/MK48H65(N,P)-35/45/55noREAD
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MK48H64/MK48H65(N,P)-35/45/55noWRIT
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MK48H64/MK48H65(N,P)-35/45/55noABSO
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SALES OFFICESAUSTRALIANSW 2027 EDGE
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Information furnished is believed t
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