memory products - Al Kossow's Bitsavers

MK48T02/12(B)-12/15/20/25WRITE MODEThe MK48T02/12 is in Write Mode whenever the Wand E inputs are held low. The start of a Write isreferenced to the latter occurring falling edge ofeither Wor E. A Write is terminated by the earlierrising edge of W or E. The ~dre~ses must be heldvalid throughout the cycle. W or E must return highfor a minimum of tWIl prior to the initiation ofanother Read or Write Cycle. Data-in must be validfor tos prior to the End of Write and remain validfor tOH afterward.Some processors thrash producing spurious WriteCycles during power-up, despite ~pli'2...ation of apower-on reset. Users should force W or E high duringpower-up to protect memory after Vcc reachesVcc (min) but before the processor stablizes.The MK48T0g[12 G input is a DON'T CARE in thewrite mode. G can be tied low and two-wire RAMcontrol can be implemented~ low on W will disablethe outputs tWEZ after W falls. Take care toavoid bus contention when operating with two-wirecontrol.FIGURE 4. WRITE-WRITE-READ TIMING~lAS ~IAWWRITEIWCWRITEREADwDa,,· Do.,VALIDINVALIDINIwEZ~rVALIDOUTAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE TIMING)(O°CSTAS70"C) (Vcc (Max)~Vcc~Vcc (Min))MK48TX2·12 MK48TX2·15 MK48TX2·20 MK48TX2·25SYM PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 120 150 200 250 nstAS Address Setup Time 0 0 0 0 nstAW Address Valid to End of Write 90 120 140 180 nstCEw Chip Enable to End of Write 75 90 120 160 nstWEW Write Enable to End of Write 75 90 120 160 nstWA Write Recovery Time 10 10 10 10 nstos Data Setup Time 35 40 60 100 nstOH Data Hold Time 0 0 0 0 nstWEz Write Enable Low to High-Z 40 50 60 80 ns4/14302