memory products - Al Kossow's Bitsavers

MK4202(Q)-20READ MODEThe MK4202 is in the Read mode whenever W isHIGH, and G is LOW provided Chip Select (5) isLOW and a true Chip Enable pattern (Eo-Ea) is applied.The 11 address inputs (Ao-A1O) define aunique index address giving access to 20 of 40,960bits of data in the static memory array. Valid datawill be present at the 20 output pins within tAVOVof the last stable address provided ChlQ Enable,Chip Select (5), and Output Enable (G) accesstimes have been met. "If Chip Enable, 5, OF Gaccess times are not met, data access will be measuredfromthe latter falling edge or limitingparameter (tEvov, tSlOV, or tGlOV)' The state QitMtag ~a 1/0 pins is controlled by the (Eo-Ea), S, G,and W input pins. The data lines may be indeterminateat tEVQX, tSlOX, or tGlOX' but will alwayshave valid data at tAVOV'READ CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(O"CsTAs70°C) (Vce = 5.0 ± 10%)STDALTSYM SYM PARAMETER MIN MAX UNITS NOTEStAVAV te Cycle Time 25 nstAVQV tAA Address Access Time 25 nstAXOX tAOH Address Output Hold Time 5 nstEVQV tEA Chip Enable Access Time 25 nstEXOX tEOH Chip Enable Output Hold Time 4 nstEVax tELZ Chip Enable TRUE to Low-Z 4 nstEXOZ. tEHZ Chip Enable FALSE to High-Z 8 nstSLaV tSA Chip Select Access Time 10 nstsHox tSOH Chip Select Output Hold Time 2 nstSlOX tSLZ Chip Select to Low-Z 3 nstSHOZ tSHZ Chip Select to High-Z 4 nstGlOV tGA Output Enable Access Time 10 nstGHOX tGOH Output Enable Output Hold Time 2 nstGlOX tGLZ Output Enable to Low-Z 2 nstGHOZ tGHZ Output Enable to High-Z 5 nsWRITE MODETheMK4202 is in the Write mode whenever W isLOW provided Chip Select (5) is LOW and a trueChip Enable pattern (Eo-Ea) is applied (G may bein either logic state). Addresses must ~ heJ.g validthroughout a write cycle, with either W.9.r S inactiveHIGH during address transitions. W may fallwith stable address, but must remain valid fortWUol/H' Since the write..!;!egins with the concurrenceof Wand 5, should W become active first, thentSlSH must be satisfied. Either W or 5 can terminatethe write cycle, therefore tOVWH or tOVSHmust be satisfied before the earlier rising edge, andtWHOX or tSHOX after the earlier rising edge. If theoutputs are active with ~ and 5 asserted LOWand with true Chip Enable, then W will return theoutputs to high impedance within tWlHZ of its failingedge.6118370