memory products - Al Kossow's Bitsavers

MK41H80(N,P)-20/25/35COMPARE, WRITE AND READ TIMINGThe MK41H80 employ!! three signals for device control.The Write Enable (WE) pin enables a Write Cycleif low and either a Compare Cycle or a ReadCycle when high. The OE pin enables a Read Cycleif low or a Compare Cycle if high. The CLR pinenables a Flash Clear Cycle when brought low.The MK41H80 begins a Compare Cycle with the applicationof a valid address (see Fi~ 2). A validMATCH is enabled when DE and WE go high inconjunction with their respective Set Up and Holdtimes. MATCH will occur tACA after a valid address,and tDCA after valid Data In. MATCH will then go invalidtACH after the address changes.The MK41H80 starts a Write Cycle with stable address~seeFigure 2). OE may be in either logicstate. WE may fall with stable addresses, and mustremain low until tAW with a duration of tWEW ' Datain must be held valid tos before and tOH after WEgoes high. MATCH will be invalid during this cycle.The MK41H80 begins a Read Cycle with stable addressesand WE high (see Figure 3). DO becomesvalid t.M.. after a valid address, and tOEA after thefall of OE. DO outputs become invalid tOH after theaddress becomes invalid or tOEZ after OE isbrought high. Ripple thro.l:!gh data access may beaccomplished by holding OE active low while strobingaddresses Ao-All' and holding CLR and WEhigh. The MATCH output will be invalid during theRead cycle.ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(O°C:5T A :570°C) (Vcc = 5.0V ±10%)·20 ·25 ·35SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStc Cycle Time 20 25 35 nstccs Compare Command Set Up Time 7 8 10 nstCCH Compare Command Hold Time 0 0 0 nstRCS Read Command (WE) Set Up Time 0 0 0 nstRCH Read Command (WE) Hold Time 0 0 0 nstAS Address Set-up Time 0 0 0 nstAW Address Stable to End of Write 16 20 30 nsCommand (WE)tAH Address Hold Time after End of Write 0 0 0 nstWEW Write Command (WE) to End of Write 16 20 30 nstos Data Set Up Time 12 13 14 nstOH Data Hold Time 0 0 0 nstOCA Data Compare AcC'llss Time 12 15 20 ns 3tACA Address Compare Access Time 20 25 35 ns 3tACH Address Compare Hold Time 5 5 5 ns 3tOCH Data Compare Hold Time 3 3 3 ns 3tOEA Output Enable (OE) Access Time 10 12 15 ns 3tOH Valid Data Out (~O) Hold Time 5 5 5 ns 3tM Address Access Time 20 25 35 ns 3tOEZ Output Enable (OE) to High-Z 7 8 10 ns 4tOEL Output Enable (OE) to Low-Z 2 2 2 ns 4tWEZ Write Enable (WE) to High-Z 8 10 13 ns 4tWEL Write Enable (WE) to Low-Z 5 5 5 ns 43/10357