memory products - Al Kossow's Bitsavers

M27256DEVICE OPERATIONThe eight modes of operations of the M27256 arelisted in the Operating Modes. A single 5V powersupply is required in the read mode. All inputs areTTL levels except for Vpp and 12V on A9 for ElectronicSignature.READ MODEThe M27256 has two control functions, both of whichmust be logically satisfied ill..Qfder to obtain dataat the outputs. Chip Enable (CE) is the power cQntroland should be used for device selection. OutputEnable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming .that addressesare stable, address access time (tACel is equalto delay from CE to output (tCE)' Data is availableat the outputs after the falling edge of OE, assumingthat CE has been low and addresses have beenstable for at least tACC-tOE'STANDBY MODEThe M27256 has a standby mode which reducesthe maximum active power current from 100 mA to40 rnA. The M27256 is placed in the standby modeby applying a TTL high signal to the CE input. Whenin the standby mode, the outputs are in a high impedancestate, independent of the OE input.TWO LINE OUTPUT CONTROLBecause EPROMs are usually used in largermemory arrays, the product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus. This assures that all deselectedmemory devices are in their low power standbymode and that the Qutput pins are only active whendata is desired from a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and transientcurrent peaks that are produced by the falling andrising edges of CEo The magnitude of this transientcurrent peaks is dependent on the output capacitiveand inductive loading of the device. The associatedtrSlnsient voltage peaks can be suppressedby complying with the two line output control andby properly selected decoupling capacitors. It isrecommended that a 1 pF ceramic capacitor beused on every device between Vcc and GND. Thisshould be a high frequency capacitor of low inherentinductance and should be placed as close tothe device as possible. In addition, a 4.7 ,..F bulkelectrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulkcapacitor should be located near where the powersupply is connected to the array. The purpose ofthe bulk capacitor is to overcome the voltage dropcaused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 13Von pin 1 (Vpp) will damagethe M27256.When delivered,andafter each erasure, all bits ofthe M27256 are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will be programmed,both "1s" and "Os" can be present in the dataword. The only way to change a "0" to a "1" is byultraviolet light erasure. The M27256 is in the progrnmmingmode when Vpp input is at 12.5V andCE and is at TTL low. The data to be programmedis applied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsM27256 EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each bytesis continually monitored to determine when it hasbeen successfully programmed. A flowchart of theM27256 Fast Programming Algorithm is shown onthe last page. The Fast Programming Algorithm utilizestwo different pulse types: init~and overprogram.The duration of the initial CE pulse (s) isone millisecond, which will then be followed by alonger overprogram pulse of length 3Xmsec. (X isan iteration counter and is equal to the number ofthe initial one millisecond pulses applied to a particularM27256 location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte areprovided for before the over program pulse is applied.The entire sequence of program pulses andbyte verifications is performed at Vcc=6V andVpp =12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original data with Vcc=Vpp=5V.5/1067