memory products - Al Kossow's Bitsavers

ST27256PDEVICE OPERATIONThe eight modes of operations of the ST27256P arelisted in the Operating Modes. A single 5V powersupply is required in the read mode. All inputs areTTL levels except for Vpp and 12V on A9 for ElectronicSignature.READ MODEThe ST27256P has two control function, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection. OutputEnable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tAccl is equalto delay from CE to output (tCE)' Data is availableat the outputs after the falling edge of OE, assumingthat CE has been low and addresses have beenstable for at least tACC-tOE'STANDBY MODEThe ST27256P has a standby mode which reducesthe maximum active power current from 100 mA to40 mA. The ST27256P is placed in the standby modeby applying a TTL high signal to the CE input. Whenin the standby mode, the outputs are in a high impedancestate, independent of the OE input.TWO LINE OUTPUT CONTROLBecause OTPs are usually used in larger memoryarrays, the product features a 2 line control functionwhich accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus. This assures that all deselectedmemory devices are in their low power standbymode and that the output pins are only active whendata is desired from a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and transientcurrent peaks that are produced by the falling andrising edges of CE. The magnitude of this transientcurrent peaks is dependent on the output capacitiveand inductive loading of the device. The associatedtransient voltage peaks can be suppressedby complying with the two line output control andby properly selected decoupling capacitors. It isrecommended that a 1 pF ceramic capaCitor beused on every device between Vcc and GND. Thisshould be a high frequency capacitor of low inherentinductance and should be placed as close tothe device as possible. In addition, a 4.7 I'F bulkelectrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulkcapacitor should be located near where the powersupply is connected to the array. The purpose ofthe bulk capacitor is to overcome the voltage dropcaused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 13Von pin 1 (Vpp) will damagethe ST27256P.When delivered, all bits of the ST27256P are in the"1" state. Data is introduced by selectively programming"Os" into the desired bit locations. Althoughonly "Os" will be programmed, both "1s" and "Os"can be present in the data word. The ST27256P isin the pro9@.mming mode when Vpp input is at12.5V and CE and is at TTL low. The data to beprogrammed is applied 8 bits in parallel to the. dataoutput pins. The levels required for the address anddata inputs are TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsST27256P EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each bytesis continually monitored to determine when it hasbeen successfully programmed. A flowchart of theST27256P Fast Programming Algorithm is shownon the last page. The Fast Programming Algorithmutilizes two different pulse types: initial and overprogram.The duration of the initial CE pulse (s) isone millisecond, which will then be followed by alonger overprogram pulse of length 3Xmsec. (X isan iteration counter and is equal to the number ofthe initial one millisecond pulses applied to a particularST27256P location), before a correct verifyoccurs. Up to 25 one-millisecond pulses per byteare provided for before the over program pulse isapplied. The entire sequence of program pulsesand byte verifications is performed at Vcc =6V andVpp=12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original data with Vcc =Vpp =5V.5/10169