memory products - Al Kossow's Bitsavers

MK41 H79(N, P)-20/25/35CLEAR CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"CsT As70"C) (Vcc = 5.0 ± 10%)MK41H79.20MK41H79·25 MK41H79·35SYMPARAMETERMINMAXMIN MAX MIN MAX UNITS NOTEStFceFlash Clear Cycle Time4050 70 nstCECChip Enable low to End of Clear4050 10 nstClPFlash Clear low to End of Clear3848 68 nstexClear to Inputs Don't Care00 0 nstCREnd of Clear to Inputs Recognized00 0 nstcwxClear to Write Enable Dori't Care00 0 nstOHCValid Data Out Hold from Clear55 5 ns 1FLASH CLEARA Flash Clear cycle sets all 16,384 bits in the RAMto logic zero. A Clear b.!!9!ns at the concurrence ofa low on Chip Enable (CE) and Flash Clear (ClR).A Clear may be ended by a high on either CE orCLR. A low on CLR has no effect if the device isFIGURE 4. lAST READ·FlASH ClEAR·FIRST WRITE------,~'Re• ..---tFCCLAST READ ADDRESS..........JI~'exdisabled (CE high). A Clear may be executed withineither a Read or a Write cycle. Figure 4 illustratesa Clear within a Read cycle. Clears withinWrite cycles are constrained only in that Write timingparameters must be observed as soon as theFlash Clear pin returns high.00II--I+-~1-.---""0-'-___ -t.1I--- fcu,---------------"l V,. MIN1\., . Iwc_FIRST WRITE ADDRESS1---' 0./CAUTION: APPLICA.IImI OF TRANSIENT LEVELS BELOW V,H MINIMUMON THE CLR INPUT DURING NORMAL OPERATIONMAY RESULT IN PARTIAL FLASH CLEAR.4110500