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M2732A32K (4K x 8) NMOS UV ERASABLE PROM• FAST ACCESS TIME:200ns MAX M2732A-2F1250ns MAX M2732AF1/M2732AF6300ns MAX M2732A-3F1450ns MAX M2732A-4F1/M2732A-4F6• 0 TO + 70°C STANDARD TEMPERATURERANGE• -40TO +85°CEXTENDEDTEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• LOW STANDBY CURRENT (35mA MAX)• INPUTS AND OUTPUTS TTL COMPATIBLEDURING READ AND PROGRAM• COMPLETELY STATICFDIP-24(Ceramic Buli's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M2732A is a 32,768-bits ultraviolet erasableand electrically programmable read-only memory(EPROM). It is organized as 4,096 words by 8 bitsand manufactured using SGS-THOMSON' Nchannel Si-Gate MOS process. The M2732A withits single + 5V power supply and with an accesstime of 200ns, is ideal for use with the high performance+ 5V microprocessors such as the Z8 * ,Z80 * and Z8000 * .The M2732A has an important feature which is theseparate output control, Q!m>ut Enable (OE) fromthe Chip Enable control (CE). The OE control elimitatesbus contention in multiple bus microprocessorsystems.The M2732A also features a standby mode whichreduces the power dissipation without increasingaccess time. The active current is 125 mA whilethe maximum standby current is only 35 mA a 70%saving. The standby modeJ.§.achieved by applyinga TTL-high signal to the CE input.The M2732A is available in a 24-lead dual in-lineceramic package glass lens (frit-seal).A7veeA6A6ASA9A4AllA3A2Al0AlCEAO 0700 0601 0502 0403PIN NAMESAO-Al1 ADDRESS INPUTCECHIP ENABLE INPUTOEOUTPUT ENABLE INPUT00-07 DATA INPUT/OUTPUTJune 1988 1/735
M2732ABLOCK DIAGRAMVcc~GNOc-.Vpp 0----+-GAIA OUTPUTJO- C7DEOUTPUTBUFFERSyDECODERGATINGAO-A11ADDRESSINPUTSDECODER32768 BtlCELL MATRIX5-6706ABSOLUTE MAXIMUM RATINGSSymbolParameterValueVIAll Input or Output voltages with respect to ground + 6to -0.6Vpp Supply voltage with respect to ground during program +22 to -0.6TambAmbient temperature under bias F1/-2FlI-3F1/-4F1 -10to+80F6/4F6-50to+95Tstg Storage temperature range -65 to + 125UnitVV°C°C°CStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.OPERATING MODES~ - -CE OElVpp Vee OUTPUTSMODE (18) (20) (24) (9-11, 13-17)READ VIL VIL +5 DOUTSTANDBY VIH Don't Care +5 High ZPROGRAM VIL Vpp +5 DINPROGRAM VERIFY VIL VIL +5 DOUTPROGRAM INHIBIT VIH Vpp +5 High Z21736
Page 2 and 3: MEMORY PRODUCTSDATABOOK1st EDITIONJ
Page 4: TABLE OF CONTENTSGENERAL INDEX Page
Page 7 and 8: GENERAL INDEXPageROM DEVICES ......
Page 10 and 11: GENERAL INFORMATIONThe SGS-THOMSON
Page 12 and 13: SELECTION GUIDECMOS UV EPROMPart Nu
Page 14 and 15: SELECTION GUIDECMOS OTP ROMPart Num
Page 16 and 17: SELECTION GUIDEZEROPOWERPart Number
Page 18 and 19: SELECTION GUIDEFAST STATIC RAMPart
Page 20 and 21: 12 32Kx8 NMOS M27256FUV EPROMPRODUC
Page 22 and 23: VFSRAMPRODUCTDESCRIPTIONSGS-THOMSON
Page 24: EPROM DEVICESNMOS UV EPROM23
Page 27 and 28: ET2716/M2716BLOCK DIAGRAM~ VPP'5V+-
Page 29 and 30: ET2716/M2716AC TEST CONDITIONSOutpu
Page 31 and 32: ET2716/M2716ERASINGThe M/ET2716 is
Page 33 and 34: ET2716/M2716SWITCHING TIME WAVEFORM
Page 38 and 39: M2732AREAD OPERATIONDC AND AC CONDI
Page 40 and 41: M2732APROGRAMMING OPERATION(l) (T a
Page 42: M2732APROGRAMMING OPERATION (Contin
Page 45 and 46: M2764ABLOCK DIAGRAMDATA OUTPUT00- 0
Page 47 and 48: M2764AREAD OPERATION (Continued)AC
Page 49 and 50: M2764ADEVICE OPERATION (Continued)T
Page 51 and 52: M2764APROGRAMMING WAVEFORMSV1HADDRE
Page 53 and 54: M2764AORDERING INFORMATIONPart Numb
Page 55 and 56: M27128ABLOCK DIAGRAMVceO--GND o--
Page 57 and 58: M27128AREAD OPERATION (Continued)AC
Page 59 and 60: M27128ADEVICE OPERATION (Continued)
Page 61 and 62: M27128APROGRAMMING WAVEFORMSIVIHADD
Page 63 and 64: M27128AORDI:RING INFORMATIONPart Nu
Page 65 and 66: M27256BLOCK DIAGRAMVeco----GNOo-
Page 67 and 68: M27256READ OPERATION (Continued)AC
Page 69 and 70: M27256DEVICE OPERATION (Continued)P
Page 71 and 72: M27256PROGRAMMING WAVEFORMSPROGRAMP
Page 73 and 74: M27256ORDERING INFORMATIONPart Numb
Page 75 and 76: M27512BLOCK DIAGRAMVee o-----?GNOO-
Page 77 and 78: M27512AC TEST CONDITIONSOutput Load
Page 79 and 80: M27512DEVICE OPERATIONS (Continued)
Page 81 and 82: M27512DEVICE OPERATION (Continued)M
Page 83 and 84: M27512PROGRAMMING OPERATION (T amb=
Page 85 and 86:
M27512M27512 DESIGN INNOVATIONS FOR
Page 87 and 88:
M27512Figure 7 - M27512 Sensing sch
Page 90:
EPROM DEVICESCMOS UV EPROM89
Page 93 and 94:
ETC2716BLOCK DIAG~AM+-- vpp+-- vcc+
Page 95 and 96:
ETC2716AC TEST CONDITIONSOutput Loa
Page 97 and 98:
ETC2716ERASING~he ETC?716 !s erased
Page 99 and 100:
ETC2716SWITCHING TIME WAVEFORMSR.ed
Page 102 and 103:
ETC273232K BIT (4K x 8) CMOS UV ERA
Page 104 and 105:
ETC2732READ OPERATIONDC CHARACTERIS
Page 106 and 107:
ETC2732DEVICE OPERATIONThe five mod
Page 108 and 109:
ETC2732PROGRAMMING WAVEFOR'''SNote:
Page 110 and 111:
ETC2732SWITCHING TIME WAVEFORMSRead
Page 112 and 113:
TS27C64AQ64K (8K x 8) CMOS UV ERASA
Page 114 and 115:
TS27C64AQREAD OPERATIONDC CHARACTER
Page 116 and 117:
TS27C64AQDEVICE OPERATIONThe seven
Page 118 and 119:
TS27C64AQAC TEST CONDITIONSInput ri
Page 120:
TS27C64AQORDERING INFORMATIONPart N
Page 123 and 124:
TS27C256QBLOCK DIAGRAMVee 0----.GND
Page 125 and 126:
TS27C256QAC TEST CONDITIONSOutput L
Page 127 and 128:
TS27C256QERASINGThe TS27C256 is era
Page 129 and 130:
TS27C256QHIGH SPEED PROGRAMMING FLO
Page 131 and 132:
,1,;'"
Page 133 and 134:
ST27C1001BLOCK DIAGRAMv P P cr-----
Page 135 and 136:
M27C1024BLOCK DIAGRAMVpp 0----:---+
Page 137 and 138:
M27C1024AC TEST CONDITIONSOutput Lo
Page 139 and 140:
M27C,1024PROGRAM INHIBITProgramming
Page 141 and 142:
M27C1024PROGRAMMING WAVEFORMSVIHADD
Page 143 and 144:
M27C1024ORDERING INFORMATIONPart Nu
Page 146 and 147:
ST2764AP64K (8K x 8) NMOS ONE TIME
Page 148 and 149:
ST2764APREAD OPERA nONDC AND AC CON
Page 150 and 151:
ST2764APDEVICE OPERATIONThe seven m
Page 152 and 153:
ST2764APPROGRAMMING OPERATION (Tamb
Page 154 and 155:
ST2764APFAST PROGRAMMING FLOWCHART9
Page 156 and 157:
ST27128AP128K (16K x 8) NMOS ONE TI
Page 158 and 159:
ST27128APREAD OPERATIONDC AND AC CO
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ST27128APDEVICE OPERATIONThe seven
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ST27128APPROGRAMMING OPERATION (Tam
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ST27128APFAST PROGRAMMING FLOWCHART
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ST27256P256K (32K x 8) NMOS ONE TIM
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ST27256PREAD OPERATIONDC AND AC CON
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ST27256PDEVICE OPERATIONThe eight m
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ST27256PPROGRAMMING OPERATION (Tamb
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ST27256PFAST PROGRAMMING FLOWCHARTF
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EPROM DEVICESCMOS OTP ROM175
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TS27C64AFN-TS27C64APBLOCK DIAGRAMVe
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TS27C64AFN-TS27C64APAC TEST CONDITI
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TS27C64FN-TS27C64APPROGRAMMINGOPERA
Page 185 and 186:
TS27C64AFN-TS27C64APHIGH SPEED PROG
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TS27C64AFN~TS27C64APORDERING INFORM
Page 189 and 190:
ST27C256FN-ST27C256PBLOCK DIAGRAMVc
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ST27C256FN·ST27C256PAC TEST CONDIT
Page 193 and 194:
ST27C256FN-ST27C256PPROGRAMMING CHA
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ST27C256FN·ST27C256PHIGH SPEED PRO
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ST27C256FN-ST27C256PORDERING INFORM
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SGS-1HOMSON~ ., L ~D©ffi1@rn[brn©
Page 202 and 203:
M8571ELECTRICAL CHARACTERISTICS (0
Page 204 and 205:
M8571S-BUS DESCRIPTION (Continued)A
Page 206 and 207:
M8571S·BUS INTERFACEThe serial, 3-
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M8571MASTER. READS AFTER SETTING WO
Page 210:
M8571ORDERING INFORMATIONPort Numbe
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M9306BLOCK DIAGRAM00DI---+-+-+-+---
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M93D6FUNCTIONAL DESCRIPTIONThe inpu
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M9306ORDERING INFORMATIONPart Numbe
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M9346BLOCK DIAGRAMDl~-r------------
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M9346FUNCTIONAL DESCRIPTIONThe inpu
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M9346INSTRUCTION SETInstruction S8
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M9346TIMING DIAGRAMS (Continued)INS
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EEPROM DEVICESCMOS EEPROM227
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ST24C02BLOCK DIAGRAMseL--~~--~-----
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ST24C02FIG. 2A· DATA TRANSFER SEQU
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ST24C02ELECTRICAL CHARACTERISTICSAC
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ST24C02FIG. 4A· PAGE WRITEBUS ACTI
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TS59C111 K BIT SERIAL CMOS EEPROM
Page 242 and 243:
TS59C11READ OPERATIONDC CHARACTERIS
Page 244 and 245:
TS59C11The READ instruction is the
Page 246 and 247:
TS59C11FIG. 5b - ERAL (Erase all) M
Page 248 and 249:
~ SGS-1HOMSONIt.. ~ L [j\I'A]O©OO@
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TS93C46READ OPERATIONDC CHARACTERIS
Page 252 and 253:
TS93C46INSTRUCTION TIMINGSREADSK ~u
Page 254:
~TS93C46ORDERING INFORMATIONPart Nu
Page 257 and 258:
ST93C56BLOCK DIAGRAMPROTECTREGISTER
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M2316H16K-BIT READ ONLY MEMORY• S
Page 262 and 263:
M2316HSTATIC ELECTRICAL CHARACTERIS
Page 264 and 265:
M2332M233332K-BIT READ ONLY MEMORY
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M2332/M2333DC AND OPERATING CHARACT
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~ SGS-11I0MSONA., L ~D©[Ri@~[lJ~©
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M2364DC AND OPERATING CHARACTERISTI
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M236564K-BIT READ ONLY MEMORY• PI
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M2365DC AND OPERATING CHARACTERISTI
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STATIC RAM DEVICES275
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MK48Z02N2(B)-12115/20/25DESCRIPTION
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MK48Z02112(B)-12115/20/25WRITE MODE
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MK48Z02/12(B)-12/15/20/25FIGURE 6.
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MK48Z02/12(B)-12/15/20/25FIGURE 7.
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MK48Z02112(B}-12115/20/25AC TEST CO
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MK48C02A/12A(K, N)·15/20/252K x 8
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MK48C02AI12A(K,N)-15/20/25OPERATION
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MK48C02A/12A(K, N)-15/20/25DATA RET
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MK48C02A112A(K,N)-15/20/25FIGURE 6.
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MK48C02A112A(K,N)-15/20/25AC TEST C
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MK48T02/12(B)-12/15120/252K x 8 ZER
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MK48T02/12(B)-12/15/20/25OPERATIONR
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MK48T02N 2(8)-12/15/20/25CLOCK OPER
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MK48T02112(B)-12/15/20/25The FT bit
Page 308 and 309:
MK48T02112(B)-12115/20/25PREDICTING
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MK48T02112(B)-12/15/20/25~redlctlng
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MK48TD2/12(B)-12115/20/25ABSOWTE MA
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M K48Z08/18/09/19(B)·15/201258K x
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MK48Z08/18/09/19(B)-15/20/25OPERATI
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MK48Z08118/09/19(B)-15/20/25AC ELEC
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MK48Z08118/09119(B)-15/20/25DATA RE
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MK48Z08118/09119(B)-15/20/25ABSOWTE
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MK48Z08/18/09/19(B)-15/20/25PACKAGE
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MKI48Z02112(B)-15/20/25DESCRIPTIONT
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M KI48Z02112(B)-15/20J25WRITE MODET
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MKI48Z02/12(B.)-15/20/25FIGURE.6. P
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MKI48Z02/12(B)-15/20/25FIGURE 7. MK
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MKI48Z02112(B)-1S/20/2SAC TEST COND
Page 338 and 339:
~ SGS-THOMSON..""! L ~o©oo@rn[!J~
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MK48T08 (8)-10/12/15/20READ MODEThe
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MK48T08 (8)-10/12/15/20AC ELECTRICA
Page 344 and 345:
MK48T08 (8)-10/12/15/20CLOCK OPERAT
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MK48T08 (B)-10112/15/20FIGURE 8. FR
Page 348 and 349:
MK48T08 (8)-10/12/15/20rhe t 10/0 f
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MK48T08 (8)-10/12/15/20PACKAGE DESC
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STATIC RAM DEVICESCACHE TAG RAM353
Page 357 and 358:
MK41 HSO(N, P)-20/25/35FIGURE 2. CO
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MK41H80(N,P)-20/25/35APPLICATIONThe
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MK41H80(N,P)-20/25/35ABSOWTE MAXIMU
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MK41 H80(N ,P)-20/25/35NORMALIZED D
Page 365 and 366:
MK41H8O(N,P),-2OI2513522 PIN "P" PA
Page 367 and 368:
MK4202(Q)-20TRUTH TABLERS S E WHi -
Page 369 and 370:
MK4202(Q)-20DEVICE DESCRIPTION AND
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MK4202(Q)-20READ MODEThe MK4202 is
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MK4202(Q)-20COMPARE CYCLE TIMINGEle
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MK4202(Q)-20FIGURE 5. W WRITE CYCLE
Page 377 and 378:
MK4202(Q)-20FIGURE 10. CHIP SELECT
Page 379 and 380:
MK4202(Q)-20FIGURE 15. LATE WRITE·
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MK4202(Q)-20FIGURE 21. RESET CYCLEr
Page 383 and 384:
MK4202(Q)-20AC TEST CONDITIONSInput
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MK48H74(N,P,E)·35/45/55DESCRIPTION
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MK48H74(N,P,E)-35/45/55WRITE MODETh
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MK48H74(N, P, E)-35/45/S5COMPARE MO
Page 391 and 392:
MK48H74(N,P,E)-35/45/55APPLICATIONT
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MK48H74(N,P,E)-35/45/55AC TEST COND
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STATIC RAM DEVICESFIFO395
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MK4501(N,K)-65/80/10112115/20a rate
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MK4501 (N, K)-65/80/1 0112/15/20REA
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MK4501 (N, K)-65/80/10/12/15/20RESE
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M K4501(N, K)-65/80110/12115/20SING
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MK4501(N,K)-65/80110112/15/20EXPANS
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MK4501(N, K)-65/80110/12/15/20COMPO
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MK4501 (N, K)-65/80110112115/20FIGU
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~ SGS-1HOMSON,."'! I. ~u©oo@rn[brn
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MK4503(N,K)-50/65/80/10/12/15/20WRI
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MK4S03(N ,K)-SO/6S/80/1 0/12/1S/20F
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MK4503(N ,K)-50/65/80110112/15/20RE
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MK4S03(N, K)-S0/6S/80110112/1S/20HA
Page 424 and 425:
MK4S03(N ,K)-SO/6S/80110112I1S/20EX
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MK4503(N, K)-50/65/80/10112/15/20CO
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MK4S03(N, K)-SO/6S/80/1 0/1211 S/20
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MK4511(N,K)-12/15/20512 x 8 CMOS Bi
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MK4511(N,K)-12115/20READ MODEThe MK
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MK4511(N,K)-12115/20DUAL PORT OPERA
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MK4511 (N,K)-12115/20IMPLEMENTATION
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MK4511(N,K)-12/15/20ABSOWTE MAXIMUM
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MK4511(N,K)-12115/20FIGURE 11. MK45
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M K4505M/4505S(N)-25/33/50DESCRIPTI
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MK4505M/4505S(N)-25/33/50AC ELECTRI
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MK4505M/4505S(N)-25/33/50FIGURE S.
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M K4505M/4505S(N)-25/33/50FIGURE 9.
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MK4505M/4505S(N)-25/33/50SIMULTANEO
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MK4505M/4505S{N)-25/33/50FIGURE 13.
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MK4505M/4505S(N)-25/33/50ABSOWTE MA
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MK4S0SM/4S0SS(N)-2S/33/S020 PIN uN"
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MK4S264/4S26S(N)-SS/70FIGURE 2. DEV
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MK45264/45265(N)-55nOAC ELECTRICAL
Page 463 and 464:
MK45264/45265(N)-55noReadlWriteThe
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MK45264/45265(N)-55noFIGURE 8. FULL
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MK4S264/4S26S(N)-SSnoFIGURE 13. TRA
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MK45264/45265(N)-55noFIGURE 18. WRI
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MK4S264/4S26S(N)-SSI7OAC TEST CONDI
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MK45264/45265(~)-5snoWidth Expansio
Page 475 and 476:
MK45264/45265(N)-55noORDERING INFOR
Page 478 and 479:
MK41H661M K41 H67(N, P)-20/25/3516K
Page 480 and 481:
MK41H66/MK41 H67(N, P)-20/25/35WRIT
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MK41H66/MK41H67(N,P)-20/25135APPLIC
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MK41H66/MK41H67{N,P)-20/25/35NORMAL
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MK41 H66/MK41 H67(N ,P)-20/25/35ORD
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MK41H681MK41H69(N,P)-20/25/354K x 4
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MK41 H68/MK41 H69(N, P)-20/25/35WRI
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MK41H68/MK41 H69(N ,P)-20/25/35APPL
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MK41 H68/MK41 H69(N ,P)-20/25/35NOR
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MK41H68/MK41H69(N,P)-20/25/35ORDERI
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t==' SGS-1HOMSON. ..,1. ~o©oo@rn[]
Page 500 and 501:
MK41 H79(N,P)·20125/35WRITE MODETh
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MK41 H79(N, P)-20/25/35ITANDBY MODE
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MK41 H79(N ,P)-20/25/35"C TEST COND
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MK41H79(N,P)-20/25/35~ORMALIZED DC
Page 508 and 509:
MK41 H87(N)-25/35/4564K x 1 CMOS ST
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MK41H87(N)-25/35/45WRITE MODEThe MK
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MK41H87(N)-25/35/45STANDBY MODEThe
Page 514 and 515:
MK41 H87(N)-25/35/45AC TEST CONDITI
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.35, 45, 55, AND 70 ns ADDRESS ACCE
Page 518 and 519:
MK48H64/MK48H65(N,P)-35/45/55noREAD
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MK48H64/MK48H65(N,P)-35/45/55noWRIT
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MK48H64/MK48H65(N,P)-35/45/55noABSO
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SALES OFFICESAUSTRALIANSW 2027 EDGE
Page 527:
Information furnished is believed t
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