memory products - Al Kossow's Bitsavers

M8571S-BUS DESCRIPTION (Continued)An addressed receiver has to generate anaknowledge after the reception of each byte; otherwisethe SDA line remains at the high level duringthe ninth clock pulse time.In this case the master transmitter can generatethe STOP information, via the SEN line, in orderto abort the transfer.COMPATIBILITY S-BUS/l2C BUS.Using the S-BUS protocol it's possible to implement"mixed" system including S-BUS/l2C busperipherals.In order to have the compability with the 12C busperipherals, the devices including the S-BUS interfacemust have their SDA and SEN pins connectedtogether as shown in figures 5a and 5b.It is also possible to use mixed S-BUS/l2C bus protocolsas showed in figure 5c. S-BUS peripheralswill only react to S-BUS protocol signals, while 12Cbus peripheral will only react to 12C bus signals.FIG. 4 - SYSTEM WITH S-BUS PERIPHERALSseLSDASEN~pS·BUSPROTOCOL5-792512seLSDASENseL- SDA'--- SENS-8USDEVICES-BU5DEVICEFig. 5 - SYSTEM WITH "MIXED" S-BUS/12C BUS PERIPHERALseLSOASEN ~seLL SDASENseLSOAseLSDAL SEN,",p5-8USPROTOCOLM8S?1[2C BUSMASTERMaS71~~SCLL--seL- SDA- SDA(a)12C BUSSLAVE(b)12C BUSSLAVE5-7929seLSOASEN,",p5-BUSIJIe BUSPROTOCOLseLSOASENMaS?1(e)-L--seLSOAPC BUSSLAVE.5/11203