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MK4511(N,K)-12/15/20ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -0.3 V to +7.0 VAmbient Operating Temperature (TAl ......................................... O°C to +70°CAmbient Storage Temperature ........................................... -55°C to +125°CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 20 mA• Stresses greater than those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedIn the operational section of this specification is not implied. Exposure to absolute maximum rating conditions forextended periods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(0 OC sT AS 70 OC)SYMPARAMETERSMINTYPMAX UNITS NOTESVccSupply Voltage4.55.05.5 V 2GNDSupply Voltage000 VVIHLogic 1 VOltage, All Inputs2.2Vcc + 0.3 V 2,3VILLogic 0 Voltage, All Inputs-0.30.8 V 2,3DC ELECTRICAL CHARACTERISTICS(OOCsTAs70OC) (Vcc = 5.0 V ± 10 percent)SYMIcc1ICC2Icc3IlLIOLVOHVOLPARAMETERSAverage Power Supply Current per PortTTL Standby Current per PortCMOS Standby Current per PortInput Leakage CurrentOutput Leakage Current (Any Output Pin)Output Logic 1 Voltage (lOUT = -1 mAlOutput LogiC 0 Voltage (lOUT = 2.1 mAlMIN-1-52.4MAX UNITS NOTES25 mA 42.5 mA 51 mA 6+1 pA- 7+5 pA- 7V 20.4 V 2CAPACITANCE(TA = 25OC, f = 1.0 MHz)SYMCICoPARAMETERSCapacitance on any Input PinCapacitance on any Output PinNOTES1. Measured with load shown in Figure 9.2. All voltages referenced to GNO.3: No more than one negative undershoot or positive overshoot of 1.5 V witha maximum pulse width of 10 ns is allowed once per cycle.4. Output buffer is deselected, both ports are active.5. All inputs = VIH.6. All inputs ""Vee - 0.2V7. Measured with GNOsVI';;Vee and outputs deselected.8. Effective capacitance is calculated as follOWS: e = .1Q.1V=3V .1V9. Output buffer is deselected.TYP UNITS NOTES4 pF 810 pF 8,99111437
MK4511(N,K)-12/15/20AC TEST CONDITIONSInput Levels ................ , ............................................ GND to 3.0 VTransition Times ................................................................. 5 nsInput Signal Timing Reference Level ................................................ 1.5 VOutput Signal Timing Reference Levels ..................................... 0.8 V and 2.2 VAmbient Temperature ....................................................... O"C to 7O"CVee ............................................................... 5.0 V ± 10 percentFIGURE 9. EQUIVALENT OUTPUT LOAD CIRCUIT+5.0 V1.8KDDEVICEUNDERTESTlKD+oo~.-=-GND• INCLUDES SCOPE AND TEST JIG.FIGURE 10. MK4511 PLASTIC LEADED CHIP CARRIER, 32 PIN (K TYPE)D01~2 PLes~ t DENOTES PIN 1.023.029 11--. 050I NOMmmDim.Min MaxA 3.048 3.556A1 1.981 2.4136 0.330 0.53361 0.660 0.812D 12.319 12.573D1 11.353 11.506D2 9.906 10.922E 14.859 15.113E1 13.893 14.046E2 12.446 13.462inchesMin Max.120 .140.078 .095.013 .021.026 .032.485 .495.447 .453.390 .430.585 .595.547 .553:490 .53010/11438
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MEMORY PRODUCTSDATABOOK1st EDITIONJ
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TABLE OF CONTENTSGENERAL INDEX Page
Page 7 and 8:
GENERAL INDEXPageROM DEVICES ......
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GENERAL INFORMATIONThe SGS-THOMSON
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SELECTION GUIDECMOS UV EPROMPart Nu
Page 14 and 15:
SELECTION GUIDECMOS OTP ROMPart Num
Page 16 and 17:
SELECTION GUIDEZEROPOWERPart Number
Page 18 and 19:
SELECTION GUIDEFAST STATIC RAMPart
Page 20 and 21:
12 32Kx8 NMOS M27256FUV EPROMPRODUC
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VFSRAMPRODUCTDESCRIPTIONSGS-THOMSON
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EPROM DEVICESNMOS UV EPROM23
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ET2716/M2716BLOCK DIAGRAM~ VPP'5V+-
Page 29 and 30:
ET2716/M2716AC TEST CONDITIONSOutpu
Page 31 and 32:
ET2716/M2716ERASINGThe M/ET2716 is
Page 33 and 34:
ET2716/M2716SWITCHING TIME WAVEFORM
Page 36 and 37:
M2732A32K (4K x 8) NMOS UV ERASABLE
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M2732AREAD OPERATIONDC AND AC CONDI
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M2732APROGRAMMING OPERATION(l) (T a
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M2732APROGRAMMING OPERATION (Contin
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M2764ABLOCK DIAGRAMDATA OUTPUT00- 0
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M2764AREAD OPERATION (Continued)AC
Page 49 and 50:
M2764ADEVICE OPERATION (Continued)T
Page 51 and 52:
M2764APROGRAMMING WAVEFORMSV1HADDRE
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M2764AORDERING INFORMATIONPart Numb
Page 55 and 56:
M27128ABLOCK DIAGRAMVceO--GND o--
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M27128AREAD OPERATION (Continued)AC
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M27128ADEVICE OPERATION (Continued)
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M27128APROGRAMMING WAVEFORMSIVIHADD
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M27128AORDI:RING INFORMATIONPart Nu
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M27256BLOCK DIAGRAMVeco----GNOo-
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M27256READ OPERATION (Continued)AC
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M27256DEVICE OPERATION (Continued)P
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M27256PROGRAMMING WAVEFORMSPROGRAMP
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M27256ORDERING INFORMATIONPart Numb
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M27512BLOCK DIAGRAMVee o-----?GNOO-
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M27512AC TEST CONDITIONSOutput Load
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M27512DEVICE OPERATIONS (Continued)
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M27512DEVICE OPERATION (Continued)M
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M27512PROGRAMMING OPERATION (T amb=
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M27512M27512 DESIGN INNOVATIONS FOR
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M27512Figure 7 - M27512 Sensing sch
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EPROM DEVICESCMOS UV EPROM89
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ETC2716BLOCK DIAG~AM+-- vpp+-- vcc+
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ETC2716AC TEST CONDITIONSOutput Loa
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ETC2716ERASING~he ETC?716 !s erased
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ETC2716SWITCHING TIME WAVEFORMSR.ed
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ETC273232K BIT (4K x 8) CMOS UV ERA
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ETC2732READ OPERATIONDC CHARACTERIS
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ETC2732DEVICE OPERATIONThe five mod
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ETC2732PROGRAMMING WAVEFOR'''SNote:
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ETC2732SWITCHING TIME WAVEFORMSRead
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TS27C64AQ64K (8K x 8) CMOS UV ERASA
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TS27C64AQREAD OPERATIONDC CHARACTER
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TS27C64AQDEVICE OPERATIONThe seven
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TS27C64AQAC TEST CONDITIONSInput ri
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TS27C64AQORDERING INFORMATIONPart N
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TS27C256QBLOCK DIAGRAMVee 0----.GND
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TS27C256QAC TEST CONDITIONSOutput L
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TS27C256QERASINGThe TS27C256 is era
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TS27C256QHIGH SPEED PROGRAMMING FLO
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,1,;'"
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ST27C1001BLOCK DIAGRAMv P P cr-----
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M27C1024BLOCK DIAGRAMVpp 0----:---+
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M27C1024AC TEST CONDITIONSOutput Lo
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M27C,1024PROGRAM INHIBITProgramming
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M27C1024PROGRAMMING WAVEFORMSVIHADD
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M27C1024ORDERING INFORMATIONPart Nu
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ST2764AP64K (8K x 8) NMOS ONE TIME
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ST2764APREAD OPERA nONDC AND AC CON
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ST2764APDEVICE OPERATIONThe seven m
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ST2764APPROGRAMMING OPERATION (Tamb
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ST2764APFAST PROGRAMMING FLOWCHART9
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ST27128AP128K (16K x 8) NMOS ONE TI
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ST27128APREAD OPERATIONDC AND AC CO
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ST27128APDEVICE OPERATIONThe seven
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ST27128APPROGRAMMING OPERATION (Tam
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ST27128APFAST PROGRAMMING FLOWCHART
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ST27256P256K (32K x 8) NMOS ONE TIM
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ST27256PREAD OPERATIONDC AND AC CON
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ST27256PDEVICE OPERATIONThe eight m
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ST27256PPROGRAMMING OPERATION (Tamb
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ST27256PFAST PROGRAMMING FLOWCHARTF
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EPROM DEVICESCMOS OTP ROM175
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TS27C64AFN-TS27C64APBLOCK DIAGRAMVe
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TS27C64AFN-TS27C64APAC TEST CONDITI
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TS27C64FN-TS27C64APPROGRAMMINGOPERA
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TS27C64AFN-TS27C64APHIGH SPEED PROG
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TS27C64AFN~TS27C64APORDERING INFORM
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ST27C256FN-ST27C256PBLOCK DIAGRAMVc
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ST27C256FN·ST27C256PAC TEST CONDIT
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ST27C256FN-ST27C256PPROGRAMMING CHA
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ST27C256FN·ST27C256PHIGH SPEED PRO
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ST27C256FN-ST27C256PORDERING INFORM
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SGS-1HOMSON~ ., L ~D©ffi1@rn[brn©
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M8571ELECTRICAL CHARACTERISTICS (0
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M8571S-BUS DESCRIPTION (Continued)A
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M8571S·BUS INTERFACEThe serial, 3-
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M8571MASTER. READS AFTER SETTING WO
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M8571ORDERING INFORMATIONPort Numbe
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M9306BLOCK DIAGRAM00DI---+-+-+-+---
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M93D6FUNCTIONAL DESCRIPTIONThe inpu
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M9306ORDERING INFORMATIONPart Numbe
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M9346BLOCK DIAGRAMDl~-r------------
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M9346FUNCTIONAL DESCRIPTIONThe inpu
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M9346INSTRUCTION SETInstruction S8
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M9346TIMING DIAGRAMS (Continued)INS
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EEPROM DEVICESCMOS EEPROM227
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ST24C02BLOCK DIAGRAMseL--~~--~-----
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ST24C02FIG. 2A· DATA TRANSFER SEQU
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ST24C02ELECTRICAL CHARACTERISTICSAC
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ST24C02FIG. 4A· PAGE WRITEBUS ACTI
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TS59C111 K BIT SERIAL CMOS EEPROM
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TS59C11READ OPERATIONDC CHARACTERIS
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TS59C11The READ instruction is the
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TS59C11FIG. 5b - ERAL (Erase all) M
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~ SGS-1HOMSONIt.. ~ L [j\I'A]O©OO@
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TS93C46READ OPERATIONDC CHARACTERIS
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TS93C46INSTRUCTION TIMINGSREADSK ~u
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~TS93C46ORDERING INFORMATIONPart Nu
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ST93C56BLOCK DIAGRAMPROTECTREGISTER
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M2316H16K-BIT READ ONLY MEMORY• S
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M2316HSTATIC ELECTRICAL CHARACTERIS
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M2332M233332K-BIT READ ONLY MEMORY
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M2332/M2333DC AND OPERATING CHARACT
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~ SGS-11I0MSONA., L ~D©[Ri@~[lJ~©
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M2364DC AND OPERATING CHARACTERISTI
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M236564K-BIT READ ONLY MEMORY• PI
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M2365DC AND OPERATING CHARACTERISTI
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STATIC RAM DEVICES275
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MK48Z02N2(B)-12115/20/25DESCRIPTION
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MK48Z02112(B)-12115/20/25WRITE MODE
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MK48Z02/12(B)-12/15/20/25FIGURE 6.
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MK48Z02/12(B)-12/15/20/25FIGURE 7.
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MK48Z02112(B}-12115/20/25AC TEST CO
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MK48C02A/12A(K, N)·15/20/252K x 8
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MK48C02AI12A(K,N)-15/20/25OPERATION
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MK48C02A/12A(K, N)-15/20/25DATA RET
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MK48C02A112A(K,N)-15/20/25FIGURE 6.
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MK48C02A112A(K,N)-15/20/25AC TEST C
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MK48T02/12(B)-12/15120/252K x 8 ZER
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MK48T02/12(B)-12/15/20/25OPERATIONR
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MK48T02N 2(8)-12/15/20/25CLOCK OPER
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MK48T02112(B)-12/15/20/25The FT bit
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MK48T02112(B)-12115/20/25PREDICTING
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MK48T02112(B)-12/15/20/25~redlctlng
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MK48TD2/12(B)-12115/20/25ABSOWTE MA
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M K48Z08/18/09/19(B)·15/201258K x
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MK48Z08/18/09/19(B)-15/20/25OPERATI
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MK48Z08118/09/19(B)-15/20/25AC ELEC
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MK48Z08118/09119(B)-15/20/25DATA RE
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MK48Z08118/09119(B)-15/20/25ABSOWTE
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MK48Z08/18/09/19(B)-15/20/25PACKAGE
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MKI48Z02112(B)-15/20/25DESCRIPTIONT
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M KI48Z02112(B)-15/20J25WRITE MODET
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MKI48Z02/12(B.)-15/20/25FIGURE.6. P
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MKI48Z02/12(B)-15/20/25FIGURE 7. MK
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MKI48Z02112(B)-1S/20/2SAC TEST COND
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~ SGS-THOMSON..""! L ~o©oo@rn[!J~
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MK48T08 (8)-10/12/15/20READ MODEThe
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MK48T08 (8)-10/12/15/20AC ELECTRICA
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MK48T08 (8)-10/12/15/20CLOCK OPERAT
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MK48T08 (B)-10112/15/20FIGURE 8. FR
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MK48T08 (8)-10/12/15/20rhe t 10/0 f
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MK48T08 (8)-10/12/15/20PACKAGE DESC
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STATIC RAM DEVICESCACHE TAG RAM353
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MK41 HSO(N, P)-20/25/35FIGURE 2. CO
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MK41H80(N,P)-20/25/35APPLICATIONThe
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MK41H80(N,P)-20/25/35ABSOWTE MAXIMU
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MK41 H80(N ,P)-20/25/35NORMALIZED D
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MK41H8O(N,P),-2OI2513522 PIN "P" PA
Page 367 and 368:
MK4202(Q)-20TRUTH TABLERS S E WHi -
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MK4202(Q)-20DEVICE DESCRIPTION AND
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MK4202(Q)-20READ MODEThe MK4202 is
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MK4202(Q)-20COMPARE CYCLE TIMINGEle
Page 375 and 376:
MK4202(Q)-20FIGURE 5. W WRITE CYCLE
Page 377 and 378:
MK4202(Q)-20FIGURE 10. CHIP SELECT
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MK4202(Q)-20FIGURE 15. LATE WRITE·
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MK4202(Q)-20FIGURE 21. RESET CYCLEr
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MK4202(Q)-20AC TEST CONDITIONSInput
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MK48H74(N,P,E)·35/45/55DESCRIPTION
Page 387 and 388: MK48H74(N,P,E)-35/45/55WRITE MODETh
Page 389 and 390: MK48H74(N, P, E)-35/45/S5COMPARE MO
Page 391 and 392: MK48H74(N,P,E)-35/45/55APPLICATIONT
Page 393 and 394: MK48H74(N,P,E)-35/45/55AC TEST COND
Page 396: STATIC RAM DEVICESFIFO395
Page 399 and 400: MK4501(N,K)-65/80/10112115/20a rate
Page 401 and 402: MK4501 (N, K)-65/80/1 0112/15/20REA
Page 403 and 404: MK4501 (N, K)-65/80/10/12/15/20RESE
Page 405 and 406: M K4501(N, K)-65/80110/12115/20SING
Page 407 and 408: MK4501(N,K)-65/80110112/15/20EXPANS
Page 409 and 410: MK4501(N, K)-65/80110/12/15/20COMPO
Page 411 and 412: MK4501 (N, K)-65/80110112115/20FIGU
Page 414 and 415: ~ SGS-1HOMSON,."'! I. ~u©oo@rn[brn
Page 416 and 417: MK4503(N,K)-50/65/80/10/12/15/20WRI
Page 418 and 419: MK4S03(N ,K)-SO/6S/80/1 0/12/1S/20F
Page 420 and 421: MK4503(N ,K)-50/65/80110112/15/20RE
Page 422 and 423: MK4S03(N, K)-S0/6S/80110112/1S/20HA
Page 424 and 425: MK4S03(N ,K)-SO/6S/80110112I1S/20EX
Page 426 and 427: MK4503(N, K)-50/65/80/10112/15/20CO
Page 428 and 429: MK4S03(N, K)-SO/6S/80/1 0/1211 S/20
Page 430 and 431: MK4511(N,K)-12/15/20512 x 8 CMOS Bi
Page 432 and 433: MK4511(N,K)-12115/20READ MODEThe MK
Page 434 and 435: MK4511(N,K)-12115/20DUAL PORT OPERA
Page 436 and 437: MK4511 (N,K)-12115/20IMPLEMENTATION
Page 440: MK4511(N,K)-12115/20FIGURE 11. MK45
Page 443 and 444: M K4505M/4505S(N)-25/33/50DESCRIPTI
Page 445 and 446: MK4505M/4505S(N)-25/33/50AC ELECTRI
Page 447 and 448: MK4505M/4505S(N)-25/33/50FIGURE S.
Page 449 and 450: M K4505M/4505S(N)-25/33/50FIGURE 9.
Page 451 and 452: MK4505M/4505S(N)-25/33/50SIMULTANEO
Page 453 and 454: MK4505M/4505S{N)-25/33/50FIGURE 13.
Page 455 and 456: MK4505M/4505S(N)-25/33/50ABSOWTE MA
Page 457 and 458: MK4S0SM/4S0SS(N)-2S/33/S020 PIN uN"
Page 459 and 460: MK4S264/4S26S(N)-SS/70FIGURE 2. DEV
Page 461 and 462: MK45264/45265(N)-55nOAC ELECTRICAL
Page 463 and 464: MK45264/45265(N)-55noReadlWriteThe
Page 465 and 466: MK45264/45265(N)-55noFIGURE 8. FULL
Page 467 and 468: MK4S264/4S26S(N)-SSnoFIGURE 13. TRA
Page 469 and 470: MK45264/45265(N)-55noFIGURE 18. WRI
Page 471 and 472: MK4S264/4S26S(N)-SSI7OAC TEST CONDI
Page 473 and 474: MK45264/45265(~)-5snoWidth Expansio
Page 475 and 476: MK45264/45265(N)-55noORDERING INFOR
Page 478 and 479: MK41H661M K41 H67(N, P)-20/25/3516K
Page 480 and 481: MK41H66/MK41 H67(N, P)-20/25/35WRIT
Page 482 and 483: MK41H66/MK41H67(N,P)-20/25135APPLIC
Page 484 and 485: MK41H66/MK41H67{N,P)-20/25/35NORMAL
Page 486 and 487: MK41 H66/MK41 H67(N ,P)-20/25/35ORD
Page 488 and 489:
MK41H681MK41H69(N,P)-20/25/354K x 4
Page 490 and 491:
MK41 H68/MK41 H69(N, P)-20/25/35WRI
Page 492 and 493:
MK41H68/MK41 H69(N ,P)-20/25/35APPL
Page 494 and 495:
MK41 H68/MK41 H69(N ,P)-20/25/35NOR
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MK41H68/MK41H69(N,P)-20/25/35ORDERI
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t==' SGS-1HOMSON. ..,1. ~o©oo@rn[]
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MK41 H79(N,P)·20125/35WRITE MODETh
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MK41 H79(N, P)-20/25/35ITANDBY MODE
Page 504 and 505:
MK41 H79(N ,P)-20/25/35"C TEST COND
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MK41H79(N,P)-20/25/35~ORMALIZED DC
Page 508 and 509:
MK41 H87(N)-25/35/4564K x 1 CMOS ST
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MK41H87(N)-25/35/45WRITE MODEThe MK
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MK41H87(N)-25/35/45STANDBY MODEThe
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MK41 H87(N)-25/35/45AC TEST CONDITI
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.35, 45, 55, AND 70 ns ADDRESS ACCE
Page 518 and 519:
MK48H64/MK48H65(N,P)-35/45/55noREAD
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MK48H64/MK48H65(N,P)-35/45/55noWRIT
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MK48H64/MK48H65(N,P)-35/45/55noABSO
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SALES OFFICESAUSTRALIANSW 2027 EDGE
Page 527:
Information furnished is believed t
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