memory products - Al Kossow's Bitsavers

MK48Z08/18/09/19(B)-15/20/25Write ModeThe MK48Z08/18/09/19 is in the Write Modewhenever the Vii and E, are low and E2(MK48Z09/19) is high. The start of a write is ~erencedto the latter occurring falling edge of W orE1, or the rising edge of E2 (MK48Z09119).~ writeis terminated by the earlier rising edge of W or E1or the falling edge of E2 (MK48Z09/19). The address~must be held valid throughout the cycle.E1 or W must return high or E2 (MK48Z09119) mustreturn low for a minimum of tWA prior to the initiationof another read or write cycle. Data-in must bevalid tos prior to the end of write and must remainvalid for tOH afterward.Because G is a Don't Care in Write Mode and a lowon Vii will return the outputs to High-Z, G can betied low and two-wire RAM control can be implemented.!-Alow on Vii will disable the outputstWEZ after W falls. Take care to avoid bus contentionwhen operating with two-wire control.FIGURE 4. WRITE CYCLE 1 (W CONTROLLED WRITE)Oq:O·OQ7COMMON 110D'N __________________ JFIGURE 5. WRITE CYCLE 2 (El CONTROLLED WRITE)00.-0°7COMMON 1/0OOUT------------~~~~--------~------------------4112316