memory products - Al Kossow's Bitsavers

MK48H74(N,P,E)-35/45/55WRITE MODEThe MK48H74 is in the Write mode whenever theVIi and 8 pins are LOW. Chip Select or VIi must beinactive during Address transitions. The Write beginswith !he concurrence of Chip Select being activewith W LOW. Therefore address setup timesare referenced to Write Enable and Chip Select astAvwL and tAVSL' and is determined to the latter occurringedge. The Write cycll!.can~e terminatedby the earlier rising edge of S or W.!Dhe Output is enabled (8 = LOW, G = LOW), thenW will return the outputs to high impedance withintWLQZ of its falling edge. Care must be taken toavoid bus contention in this type of operation. Datainmust be valid fortovwH to the rising edge ofWrite Enable, or to the rising edge of S, whicheveroccurs fi~t, a'l9 remain valid tWHOX after the risingedge of S or W.WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°C:sTA:s70°C) (Vee = 5.0 ±10%)SYMBOLS 48H74-35 48H74-45 48H74-55ALT. STD. PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStwe tAVAV Write Cycle Time 35 45 55 nstAS tAVWL Address Set-up Time to 0 0 0 nsWrite Enable LowtAS tAVSL Address Set-up Time to 0 0 0 nsChip SelecttAW tAVWH Address Valid to End 25 35 45 nsof WritetWEW tWLWH Write Pulse Width 25 35 45 nstAH tWHAX Address Hold Time after 0 0 0 nsEnd of Writetesw tSLSH Chip Select to End 25 35 45 nsof WritetWR tSHAX Write Recovery Time 0 0 0 nsto Chip Deselecttow tOVWH Data Valid to End of 25 30 30 nsWritetOH tWHDX Data Hold Time 0 0 0 nstWEL tWHOX Write High to Output 0 0 0 ns 2Low-Z (Active)tWEZ tWLQZ Write Enable to Output 15 20 25 ns 2High-Z4111386