memory products - Al Kossow's Bitsavers

MK4202(Q)-20COMPARE CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(O°C:sTA:s70°C) (Vcc = 5.0 ± 10%)STD ALTSYM SYM PARAMETER MINtAVCV tACA Address Compare Access TimetAXCX tACOH Address Compare Output Hold Time 5tovcv tOCA Tag Data Compare Access Timetoxcx tOCH Tag Data Compare Hold Time 2tWLCH tWCH W LOW to Compare HIGHtWHCX tWCOH W Compare Output Hold Time 3tWLCX tWCLZ W to Compare Low-Z 3twHCV twcv W to Compare ValidtGLCH tGCH G LOW to Compare HIGHtGHCX tCGOH G Compare Output Hold Time 3tGLCX tGCLZ G to Compare Low-Z 3tGHCV tGCV G to Compare ValidtEVCV tECA E True to Compare Access TimetEXCX tECOH E False Compare Hold Time 4tEVCX tECLZ E True 10 Compare Low-Z 4tEXCZ tECHZ E False to Compare High-ZtCGL·CV tCGA CGX to Compare Access TimetCGH·CX tCGOH CGx Compare Hold Time 2tCGL·CX tCGLZ CGX LOW to Compare Low-Z 2tCGH-CZ tCGHZ CGX HIGH to Compare High-ZMAX UNITS NOTES20 nsns16 nsns10 nsnsns8 ns10 nsnsns8 ns20 nsnsns8 ns8 nsnsns8 nsNOTE: E = Enable Inputs (EO-E3).RESET MODEThe MK4202 allows an asynchronous resetwhenever AS is LOW regardless of the logic stateon the other input pins. Reset clears all internalRAM bits in CDOo (2048 bits) to a logic zero. Thisoutput can be used as a valid tag bit to ensure a validcompare miss or hit condition. It should be notedthat a valid write cycle is not allowed during a resetcycle (W = LOW, S = LOW, RS = LOW, and ChipEnable is true). The state of the data outputs is delermJrles!by th~nput control logic pins: Chip Enable,S, G, and W (see truth table). Should a resetoccur during a valid compare cycle, and the CDOovalid tag bit is set to a logic (1), then C.JL!Vill goLOW at tRSL-CL from the falling edge of RS.8/18372