memory products - Al Kossow's Bitsavers

MK48H74(N,P,E)·35/45/55DESCRIPTIONThe MK48H74 is a 65,636-bit fast static cache TA­GRAM organized as 8K x 8 bits. It is fabricated usingSGB-THOMSON's low power, high performance,CMOS technology. The MK48H74 faatur8s fully staticoperation requiring no external clocks or timingstrobes, and equal address access and cycle times.The device requires a single +5V ±10 percent sup­. ply, and is fully TTL compatible.The MK48H74 has a fast Chip Select control for highspeed operation to Match Compare valid, anddevice selectldeselect operations. Additionally, theMK48H74 provides a Reset Clear, and Match comparepin. The Reset Clear input provides an asynchronousRAM clear control which clears all internalRAM bits to zero in only two cycles. The MATCHoutput features an open-drain for wired OR operation.During a match compare cycle, an on-board8-bit comparator compares the Data Inputs (8-bitTAG) at the specified address index (A()"A1~ to theinternal RAM data. If a match exists, the MATCHoutput issues a HIGH match valid signal. If a misscondition exists, where at least one bit of TAG datadoes not match the internal RAM, then the MATCHoutput issues a LOW miss signal.OPERATIONSREAD MODEThe MK46H74 is in the read mode whenever WriteEnable f!N) is HIGH with Output Enable (G) LOW,and Chip Select (5) is active. This provides accessto data from eight of 65,536 locations in the staticmemory array. The unique address specified by the13 Address Inputs defines which one of the 81928-bit bytes is to be accessed.Valid data will be available at the eight Output pinswithin tAvov after the last stable address, providingG is LOW, and 5 is LOW. If Chip Select or OutputEnable access times are not met, data access willbe measured from the limiting parameter (t~LQ\L or~LQV) rather than the address. The state of tne DQpins is controlled by the 5, G, and W control signals.Data out may be indeterminate at tslox andtGlOX' but data lines will always be valid at tAvov'READ CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"CsTAs70"C) (Vee = 5.0 ±10%)SYMBOLS 48H74·35 48H74·45 48H74·55ALT. STD. PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTESt~c tAVAV Read Cycle Time 35 45 55 nstM tAVOV Address Access Time 35 45 55 ns 1tcSA tSlQV Chip Select Access Time 20 25 30 nstOEA ~lQV Output Enable Access 20 25 30 ns 1TimeteSl tSlOX Chip Select to Output 5 5 5 nsLow-ZtoEl ~LOX Output Enable to Low-Z 0 0 0 nstesz tSHQZ Chip Select to High-Z 15 20 25 nstoEZ ~HQZ Output Enable to High-Z 15 20 25 ns 2toH tAXQX Output Hold From Address 3 3 3 ns 1Change2N1384