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TS27C64AFN-TS27C64APDEVICE OPERATIONThe seven modes of operation of the TS27C64Aare listed in the Operating Modes table. A singleSV power supply is required in the read mode. Allinputs are TTL levels except for Vpp.READ MODEThe TS27C64A has two control functions, both ofwich must be logically active in order to obtain dataat the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tACC) is equal tothe delay from CE to Output (tCE). Data is availableat the oUJrults after a delay of tOE from the fallingedge of OE, assuming that CE has been low andaddresses have been stable for at least tAcc-tOE.STANDBY MODEThe TS27C64A has a standby mode which reducesthe maximum power dissipation to S.S mW. TheTS27C64A is placed in the standby mode by applyinga TTL high signal to the CE input. When instandby mode, the outputs ar~a high impedancestate, independent of the OE input.OUTPUT OR-TYINGBecause OTPs are usually used in larger memoryarrays, we have provided two control lines whichaccomodate this multiple memory connection. Thetwo control lines allow for:a) the lowest possible memory power dissipation,andb) complete assurance that output bus contentionwill not occur.To use these control lines most efficiently, CEshould be decoded and used as the primary deviceselecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus. This assures that all deselected memorydevices are in their low power standby modesand that the output pins are active only whendata is desired from a particular memory device.PROGRAMMINGCaution: Exceeding 14Von Vpp pin will damagethe TS27C64A.Initially, all bits of the TS27C64A are in the" 1" state.Data is introduced by selectively programming"Os" into the desired bit locations. Although only"Os" will be programmed, both "1s" and "Os" canbe presented in the data word.The TS27C64A is in the programming mode whenthe Vpp input is at 12.S V and CE and PGM areboth at TTL Low. It is required that a 0.1 /,F capacitorbe placed across Vpp, VCC and ground tosuppress spurious voltage transients which may damagethe device. The data to be programmed isapplied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TTL.Programming of multiple TS27C64As in parallelwith the same data can be easily accomplished dueto the simplicity of the programming requirements.Like inputs of the parallel TS27C64As may be connectedtogether when they are programmed withthe same data. A low level TTL pulse applied tothe PGM input programs the paralleledTS27C64As.HIGH SPEED PROGRAMMINGThe high speed programming algorithm describedin the flow chart rapidly programs TS27C64A usingan efficient and reliable method particularly suitedto the production programming environment. Typicalprogramming times for individual devices areon the order of 1 minute.PROGRAM INHIBITProgramming of multiple TS27C64As in parallelwith different data is also easily accomplished..Qyusing the program inhibit mode. A high level on CEor PGM inputs inhibits the other TS27C64As fromfrom being programmed. Except for CE, all likeinputs (including OE) of the parallel TS27C64Asmay be comm
TS27C64FN-TS27C64APPROGRAMMINGOPERATIONS(1)(T amb = 25 ± 5°C, VCC = 6.0V ± 0.25V, Vpp = 12.5V ± 0.3V)DC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsMin.ValuesTyp.Max.UnitII Input Current (all inputs) VI = VIL or VIHVIL Input Low Level (all inputs) -0.1VIH Input High Level 2.0VOL Output low voltage during verify IOL=2.1 mAVOH Output high voltage during verify IOH= -400 pA 2.4lee3Vee Supply current(Program & Verify)IpP2 Vpp supply current (Program) CE=VIL=PGM100.8Vee+ 10.453030pAVVVVmAmAAC CHARACTERISTICSSymbol Parameter Test ConditionstAS Address Set-up Time 2tOES OE Set-up Time 2tos Data Set-up Time 2tAH Address Hold Time 0tOH Data Hold Time 2tOFP Output enable to output float delay 0tvps Vpp set-up time 2tves Vee set-up time 2Min.Valuestpw PGM initial program pulse width 0.95 1.0topW
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MEMORY PRODUCTSDATABOOK1st EDITIONJ
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TABLE OF CONTENTSGENERAL INDEX Page
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GENERAL INDEXPageROM DEVICES ......
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GENERAL INFORMATIONThe SGS-THOMSON
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SELECTION GUIDECMOS UV EPROMPart Nu
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SELECTION GUIDECMOS OTP ROMPart Num
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SELECTION GUIDEZEROPOWERPart Number
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SELECTION GUIDEFAST STATIC RAMPart
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12 32Kx8 NMOS M27256FUV EPROMPRODUC
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VFSRAMPRODUCTDESCRIPTIONSGS-THOMSON
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EPROM DEVICESNMOS UV EPROM23
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ET2716/M2716BLOCK DIAGRAM~ VPP'5V+-
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ET2716/M2716AC TEST CONDITIONSOutpu
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ET2716/M2716ERASINGThe M/ET2716 is
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ET2716/M2716SWITCHING TIME WAVEFORM
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M2732A32K (4K x 8) NMOS UV ERASABLE
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M2732AREAD OPERATIONDC AND AC CONDI
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M2732APROGRAMMING OPERATION(l) (T a
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M2732APROGRAMMING OPERATION (Contin
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M2764ABLOCK DIAGRAMDATA OUTPUT00- 0
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M2764AREAD OPERATION (Continued)AC
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M2764ADEVICE OPERATION (Continued)T
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M2764APROGRAMMING WAVEFORMSV1HADDRE
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M2764AORDERING INFORMATIONPart Numb
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M27128ABLOCK DIAGRAMVceO--GND o--
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M27128AREAD OPERATION (Continued)AC
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M27128ADEVICE OPERATION (Continued)
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M27128APROGRAMMING WAVEFORMSIVIHADD
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M27128AORDI:RING INFORMATIONPart Nu
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M27256BLOCK DIAGRAMVeco----GNOo-
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M27256READ OPERATION (Continued)AC
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M27256DEVICE OPERATION (Continued)P
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M27256PROGRAMMING WAVEFORMSPROGRAMP
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M27256ORDERING INFORMATIONPart Numb
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M27512BLOCK DIAGRAMVee o-----?GNOO-
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M27512AC TEST CONDITIONSOutput Load
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M27512DEVICE OPERATIONS (Continued)
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M27512DEVICE OPERATION (Continued)M
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M27512PROGRAMMING OPERATION (T amb=
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M27512M27512 DESIGN INNOVATIONS FOR
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M27512Figure 7 - M27512 Sensing sch
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EPROM DEVICESCMOS UV EPROM89
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ETC2716BLOCK DIAG~AM+-- vpp+-- vcc+
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ETC2716AC TEST CONDITIONSOutput Loa
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ETC2716ERASING~he ETC?716 !s erased
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ETC2716SWITCHING TIME WAVEFORMSR.ed
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ETC273232K BIT (4K x 8) CMOS UV ERA
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ETC2732READ OPERATIONDC CHARACTERIS
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ETC2732DEVICE OPERATIONThe five mod
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ETC2732PROGRAMMING WAVEFOR'''SNote:
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ETC2732SWITCHING TIME WAVEFORMSRead
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TS27C64AQ64K (8K x 8) CMOS UV ERASA
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TS27C64AQREAD OPERATIONDC CHARACTER
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TS27C64AQDEVICE OPERATIONThe seven
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TS27C64AQAC TEST CONDITIONSInput ri
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TS27C64AQORDERING INFORMATIONPart N
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TS27C256QBLOCK DIAGRAMVee 0----.GND
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TS27C256QAC TEST CONDITIONSOutput L
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TS27C256QERASINGThe TS27C256 is era
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TS27C256QHIGH SPEED PROGRAMMING FLO
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Page 133 and 134: ST27C1001BLOCK DIAGRAMv P P cr-----
Page 135 and 136: M27C1024BLOCK DIAGRAMVpp 0----:---+
Page 137 and 138: M27C1024AC TEST CONDITIONSOutput Lo
Page 139 and 140: M27C,1024PROGRAM INHIBITProgramming
Page 141 and 142: M27C1024PROGRAMMING WAVEFORMSVIHADD
Page 143 and 144: M27C1024ORDERING INFORMATIONPart Nu
Page 146 and 147: ST2764AP64K (8K x 8) NMOS ONE TIME
Page 148 and 149: ST2764APREAD OPERA nONDC AND AC CON
Page 150 and 151: ST2764APDEVICE OPERATIONThe seven m
Page 152 and 153: ST2764APPROGRAMMING OPERATION (Tamb
Page 154 and 155: ST2764APFAST PROGRAMMING FLOWCHART9
Page 156 and 157: ST27128AP128K (16K x 8) NMOS ONE TI
Page 158 and 159: ST27128APREAD OPERATIONDC AND AC CO
Page 160 and 161: ST27128APDEVICE OPERATIONThe seven
Page 162 and 163: ST27128APPROGRAMMING OPERATION (Tam
Page 164 and 165: ST27128APFAST PROGRAMMING FLOWCHART
Page 166 and 167: ST27256P256K (32K x 8) NMOS ONE TIM
Page 168 and 169: ST27256PREAD OPERATIONDC AND AC CON
Page 170 and 171: ST27256PDEVICE OPERATIONThe eight m
Page 172 and 173: ST27256PPROGRAMMING OPERATION (Tamb
Page 174 and 175: ST27256PFAST PROGRAMMING FLOWCHARTF
Page 176: EPROM DEVICESCMOS OTP ROM175
Page 179 and 180: TS27C64AFN-TS27C64APBLOCK DIAGRAMVe
Page 181: TS27C64AFN-TS27C64APAC TEST CONDITI
Page 185 and 186: TS27C64AFN-TS27C64APHIGH SPEED PROG
Page 187 and 188: TS27C64AFN~TS27C64APORDERING INFORM
Page 189 and 190: ST27C256FN-ST27C256PBLOCK DIAGRAMVc
Page 191 and 192: ST27C256FN·ST27C256PAC TEST CONDIT
Page 193 and 194: ST27C256FN-ST27C256PPROGRAMMING CHA
Page 195 and 196: ST27C256FN·ST27C256PHIGH SPEED PRO
Page 197 and 198: ST27C256FN-ST27C256PORDERING INFORM
Page 200 and 201: SGS-1HOMSON~ ., L ~D©ffi1@rn[brn©
Page 202 and 203: M8571ELECTRICAL CHARACTERISTICS (0
Page 204 and 205: M8571S-BUS DESCRIPTION (Continued)A
Page 206 and 207: M8571S·BUS INTERFACEThe serial, 3-
Page 208 and 209: M8571MASTER. READS AFTER SETTING WO
Page 210: M8571ORDERING INFORMATIONPort Numbe
Page 213 and 214: M9306BLOCK DIAGRAM00DI---+-+-+-+---
Page 215 and 216: M93D6FUNCTIONAL DESCRIPTIONThe inpu
Page 217 and 218: M9306ORDERING INFORMATIONPart Numbe
Page 219 and 220: M9346BLOCK DIAGRAMDl~-r------------
Page 221 and 222: M9346FUNCTIONAL DESCRIPTIONThe inpu
Page 223 and 224: M9346INSTRUCTION SETInstruction S8
Page 225 and 226: M9346TIMING DIAGRAMS (Continued)INS
Page 228: EEPROM DEVICESCMOS EEPROM227
Page 231 and 232: ST24C02BLOCK DIAGRAMseL--~~--~-----
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ST24C02FIG. 2A· DATA TRANSFER SEQU
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ST24C02ELECTRICAL CHARACTERISTICSAC
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ST24C02FIG. 4A· PAGE WRITEBUS ACTI
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TS59C111 K BIT SERIAL CMOS EEPROM
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TS59C11READ OPERATIONDC CHARACTERIS
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TS59C11The READ instruction is the
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TS59C11FIG. 5b - ERAL (Erase all) M
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~ SGS-1HOMSONIt.. ~ L [j\I'A]O©OO@
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TS93C46READ OPERATIONDC CHARACTERIS
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TS93C46INSTRUCTION TIMINGSREADSK ~u
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~TS93C46ORDERING INFORMATIONPart Nu
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ST93C56BLOCK DIAGRAMPROTECTREGISTER
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M2316H16K-BIT READ ONLY MEMORY• S
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M2316HSTATIC ELECTRICAL CHARACTERIS
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M2332M233332K-BIT READ ONLY MEMORY
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M2332/M2333DC AND OPERATING CHARACT
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~ SGS-11I0MSONA., L ~D©[Ri@~[lJ~©
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M2364DC AND OPERATING CHARACTERISTI
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M236564K-BIT READ ONLY MEMORY• PI
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M2365DC AND OPERATING CHARACTERISTI
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STATIC RAM DEVICES275
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MK48Z02N2(B)-12115/20/25DESCRIPTION
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MK48Z02112(B)-12115/20/25WRITE MODE
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MK48Z02/12(B)-12/15/20/25FIGURE 6.
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MK48Z02/12(B)-12/15/20/25FIGURE 7.
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MK48Z02112(B}-12115/20/25AC TEST CO
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MK48C02A/12A(K, N)·15/20/252K x 8
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MK48C02AI12A(K,N)-15/20/25OPERATION
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MK48C02A/12A(K, N)-15/20/25DATA RET
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MK48C02A112A(K,N)-15/20/25FIGURE 6.
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MK48C02A112A(K,N)-15/20/25AC TEST C
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MK48T02/12(B)-12/15120/252K x 8 ZER
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MK48T02/12(B)-12/15/20/25OPERATIONR
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MK48T02N 2(8)-12/15/20/25CLOCK OPER
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MK48T02112(B)-12/15/20/25The FT bit
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MK48T02112(B)-12115/20/25PREDICTING
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MK48T02112(B)-12/15/20/25~redlctlng
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MK48TD2/12(B)-12115/20/25ABSOWTE MA
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M K48Z08/18/09/19(B)·15/201258K x
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MK48Z08/18/09/19(B)-15/20/25OPERATI
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MK48Z08118/09/19(B)-15/20/25AC ELEC
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MK48Z08118/09119(B)-15/20/25DATA RE
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MK48Z08118/09119(B)-15/20/25ABSOWTE
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MK48Z08/18/09/19(B)-15/20/25PACKAGE
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MKI48Z02112(B)-15/20/25DESCRIPTIONT
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M KI48Z02112(B)-15/20J25WRITE MODET
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MKI48Z02/12(B.)-15/20/25FIGURE.6. P
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MKI48Z02/12(B)-15/20/25FIGURE 7. MK
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MKI48Z02112(B)-1S/20/2SAC TEST COND
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~ SGS-THOMSON..""! L ~o©oo@rn[!J~
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MK48T08 (8)-10/12/15/20READ MODEThe
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MK48T08 (8)-10/12/15/20AC ELECTRICA
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MK48T08 (8)-10/12/15/20CLOCK OPERAT
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MK48T08 (B)-10112/15/20FIGURE 8. FR
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MK48T08 (8)-10/12/15/20rhe t 10/0 f
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MK48T08 (8)-10/12/15/20PACKAGE DESC
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STATIC RAM DEVICESCACHE TAG RAM353
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MK41 HSO(N, P)-20/25/35FIGURE 2. CO
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MK41H80(N,P)-20/25/35APPLICATIONThe
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MK41H80(N,P)-20/25/35ABSOWTE MAXIMU
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MK41 H80(N ,P)-20/25/35NORMALIZED D
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MK41H8O(N,P),-2OI2513522 PIN "P" PA
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MK4202(Q)-20TRUTH TABLERS S E WHi -
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MK4202(Q)-20DEVICE DESCRIPTION AND
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MK4202(Q)-20READ MODEThe MK4202 is
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MK4202(Q)-20COMPARE CYCLE TIMINGEle
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MK4202(Q)-20FIGURE 5. W WRITE CYCLE
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MK4202(Q)-20FIGURE 10. CHIP SELECT
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MK4202(Q)-20FIGURE 15. LATE WRITE·
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MK4202(Q)-20FIGURE 21. RESET CYCLEr
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MK4202(Q)-20AC TEST CONDITIONSInput
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MK48H74(N,P,E)·35/45/55DESCRIPTION
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MK48H74(N,P,E)-35/45/55WRITE MODETh
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MK48H74(N, P, E)-35/45/S5COMPARE MO
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MK48H74(N,P,E)-35/45/55APPLICATIONT
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MK48H74(N,P,E)-35/45/55AC TEST COND
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STATIC RAM DEVICESFIFO395
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MK4501(N,K)-65/80/10112115/20a rate
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MK4501 (N, K)-65/80/1 0112/15/20REA
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MK4501 (N, K)-65/80/10/12/15/20RESE
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M K4501(N, K)-65/80110/12115/20SING
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MK4501(N,K)-65/80110112/15/20EXPANS
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MK4501(N, K)-65/80110/12/15/20COMPO
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MK4501 (N, K)-65/80110112115/20FIGU
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~ SGS-1HOMSON,."'! I. ~u©oo@rn[brn
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MK4503(N,K)-50/65/80/10/12/15/20WRI
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MK4S03(N ,K)-SO/6S/80/1 0/12/1S/20F
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MK4503(N ,K)-50/65/80110112/15/20RE
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MK4S03(N, K)-S0/6S/80110112/1S/20HA
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MK4S03(N ,K)-SO/6S/80110112I1S/20EX
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MK4503(N, K)-50/65/80/10112/15/20CO
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MK4S03(N, K)-SO/6S/80/1 0/1211 S/20
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MK4511(N,K)-12/15/20512 x 8 CMOS Bi
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MK4511(N,K)-12115/20READ MODEThe MK
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MK4511(N,K)-12115/20DUAL PORT OPERA
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MK4511 (N,K)-12115/20IMPLEMENTATION
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MK4511(N,K)-12/15/20ABSOWTE MAXIMUM
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MK4511(N,K)-12115/20FIGURE 11. MK45
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M K4505M/4505S(N)-25/33/50DESCRIPTI
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MK4505M/4505S(N)-25/33/50AC ELECTRI
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MK4505M/4505S(N)-25/33/50FIGURE S.
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M K4505M/4505S(N)-25/33/50FIGURE 9.
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MK4505M/4505S(N)-25/33/50SIMULTANEO
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MK4505M/4505S{N)-25/33/50FIGURE 13.
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MK4505M/4505S(N)-25/33/50ABSOWTE MA
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MK4S0SM/4S0SS(N)-2S/33/S020 PIN uN"
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MK4S264/4S26S(N)-SS/70FIGURE 2. DEV
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MK45264/45265(N)-55nOAC ELECTRICAL
Page 463 and 464:
MK45264/45265(N)-55noReadlWriteThe
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MK45264/45265(N)-55noFIGURE 8. FULL
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MK4S264/4S26S(N)-SSnoFIGURE 13. TRA
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MK45264/45265(N)-55noFIGURE 18. WRI
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MK4S264/4S26S(N)-SSI7OAC TEST CONDI
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MK45264/45265(~)-5snoWidth Expansio
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MK45264/45265(N)-55noORDERING INFOR
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MK41H661M K41 H67(N, P)-20/25/3516K
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MK41H66/MK41 H67(N, P)-20/25/35WRIT
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MK41H66/MK41H67(N,P)-20/25135APPLIC
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MK41H66/MK41H67{N,P)-20/25/35NORMAL
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MK41 H66/MK41 H67(N ,P)-20/25/35ORD
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MK41H681MK41H69(N,P)-20/25/354K x 4
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MK41 H68/MK41 H69(N, P)-20/25/35WRI
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MK41H68/MK41 H69(N ,P)-20/25/35APPL
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MK41 H68/MK41 H69(N ,P)-20/25/35NOR
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MK41H68/MK41H69(N,P)-20/25/35ORDERI
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t==' SGS-1HOMSON. ..,1. ~o©oo@rn[]
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MK41 H79(N,P)·20125/35WRITE MODETh
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MK41 H79(N, P)-20/25/35ITANDBY MODE
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MK41 H79(N ,P)-20/25/35"C TEST COND
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MK41H79(N,P)-20/25/35~ORMALIZED DC
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MK41 H87(N)-25/35/4564K x 1 CMOS ST
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MK41H87(N)-25/35/45WRITE MODEThe MK
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MK41H87(N)-25/35/45STANDBY MODEThe
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MK41 H87(N)-25/35/45AC TEST CONDITI
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.35, 45, 55, AND 70 ns ADDRESS ACCE
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MK48H64/MK48H65(N,P)-35/45/55noREAD
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MK48H64/MK48H65(N,P)-35/45/55noWRIT
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MK48H64/MK48H65(N,P)-35/45/55noABSO
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SALES OFFICESAUSTRALIANSW 2027 EDGE
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Information furnished is believed t
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