memory products - Al Kossow's Bitsavers

MK48T08 (8)-10/12/15/20Calibrating the ClockThe MK48T08 is driven by a quartz controlled oscillatorwith a nominal frequency of 32768 Hz. Thecrystal is mounted in the tophat along with the battery.A typical MK48T08 is accurate within ± 1 minuteper month at 25°C without calibration. Thedevices are tested not to exceed 35 PPM (parts permillion) oscillator frequency error at 25°C, whichcomes to about ± 1.53 minutes per month. Of coursethe oscillation rate of any crystal changes withtemperature. Figure 6. shows the frequency errorthat can be expected at various temperatures.Most clock chips compensate for crystal frequencyand temperature shift error with cumbersometrim capacitors. The MK48T08 design, however,employs periodic counter correction. The calibrationcircuit adds or subtracts counts from the oscillatordivider circuit at the divide by 128 stage, asshown in figure 7. The number of times pulses areblanked (subtracted, negative calibration) or split(added, positive calibration) depends upon the valueloaded into the five bit Calibration byte foundin the Control Register. Adding counts speeds theclock up, subtracting counts slows the clock down.FIGURE 7. ADJUSTING THE DIVIDE BY 128NORMAL ~POSITIVE n n n n nCLAIBRATION.J L.J U L.J L.J LNEGATIVE n n nCALIBRATION .J ~ L.J LThe Calibration byte occupies the five lower orderbits in the Control register. This byte can be setto represent any value between 0 and 31 in binaryform. The sixth bit is a sign bit; "1" indicates positivecalibration, "0" indicates negative calibration.Calibration occurs within a 64 minute cycle. Thefirst 62 minutes in the cycle may, once per minute,have one second either shortened or lengthenedby 256 oscillator cycles, that is one tick of thedivide by 128 stage of the clock chain. If a binary"1" is loaded into the register, only the first 4minutes in the 64 minute cycle will be modified; ifa binary 6 is loaded, the first 24 will be affected andso on.Therefore, each calibration step has the effect ofadding or subtracting 512 oscillator cycles for every125,829, 120 actual oscillator cycles, that is 4.068PPM of adjustment per calibration step gin the user126.14 PPM calibration range. Assuming that theoscillator is in fact running at exactly 32768 Hz,each of the 31 increments in the Calibration bytewould represent 10.7 seconds per month.Two methods are available for ascertaining howmuch calibration a given MK48T08 may require.The first involves simply setting the clock, lettingit run for a month and comparing it to a known accuratereference (like WWV broadcasts). While thatmay seem crude, it allows the designer to give theend user the ability to calibrate his clock as his environmentmay require, even after the final productis packaged in a non-user serviceable enclosure.All the designer has to do is provide a simple utilitythat accessed the Calibration byte. The utilitycould even be menu driven and made foolproof.The second approach is better suited to a manufacturingenvironment, and involves the use of sometest equipment. When the Frequency Test (FT.)bit, the seventh-most significant bit in the day Register,is set to a "1", and the oscillator is runningat 32768 Hz, the LSB (DOO) of the Seconds Registerwill toggle at a 512 Hz. Any deviation from 512Hz indicates the degree and direction of oscillatorfrequency shift at the test temperature. For example,a reading of 512.01024 Hz would indicate a+ 20 PPM oscillator frequency error, requiring a-5 (000101) to be loaded into the Calibration Bytefor correction. Note that setting or changing the CalibrationByte does not affect the Frequency Testoutput frequency. The device must be selected andaddresses must stable at Address 1 FF9 when readingthe 512 Hz on DOO.The FT. bit must be set using the same methodused to set the clock, using the Write bit. The LSBof the Seconds Register is monitored by holdingthe MK48T08 in an extended read of the SecondsRegister, without having the Read bit set. The FT.bit MUST be reset to a "0" for normal clock operationsto resume.8/13344