memory products - Al Kossow's Bitsavers

MK4505M/4505S{N)·25/33/50VERY HIGH-SPEED CMOS CLOCKED FIFOPRELIMINARY DATA.1024 x 5 ORGANIZATION• VERY HIGH PERFORMANCEPart No. Cycle Time Cycle AccessFrequency Time4505-25 25 ns 40 MHz 15 ns4505-33 33 ns 30 MHz 20 ns4505-50 50 ns 20 MHz 25 ns• RISING EDGE TRIGGERED CLOCK INPUTS• SUPPORTS FREE-RUNNING 40% TO 60%DUTY CYCLE CLOCK INPUTS• SEPARATE READ AND WRITE ENABLEINPUTS• BiPORT'" RAM ARCHITECTURE ALLOWS FUL­LY ASYNCHRONOUS AND SIMULTANEOUSREADIWRITE OPERATION• CASCADABLE TO ANY DEPTH WITH NO AD­DITIONAL LOGIC• WIDTH EXPANDABLE TO MORE THAN 40 BITSWITH NO ADDITIONAL LOGIC• HALF FULL STATUS FLAG• FULL AND EMPTY FLAGS, ALMOST FULL,ALMOST EMPTY, INPUT READY, OUTPUTVALID STATUS FLAGS (4505M)~ (~'I:'20' . . . I" .'! I' ' '.1 'NDlp·20(Plastic Package)NDIP-24(Plastic Package)FIGURE 1. PIN CONFIGURATION2. V" 20 V"D, 2 23 CKw D, 2 19D, 3 22 WE, D, 3 18D,•21 FF D,•17D, 5 20 DR D, 5 MK4505S 1.AE• MK4505M 1. HF As •15As 7 18 AF RE, 7 14av 8 17 a, RE, 8 13EF •1. a, CK,•12RE, 1. 15 a, v"eK, 11 1. a,12 13 a,v"10 11CKwWE,WE,HFa,a,a,a,a,• FULLY TTL COMPATIBLE• 300 MIL PLASTIC DIPPIN NAMESDo - D40 0 - 0 4CKw, CK RWE,RE,ASHFSupersedes publication for January 1988.June 1988. Data Input- Data Output- Write and Read Clock- Write Enable Input 1- Read Enable Input 1- Reset (Active Low)- Half Full Flag- +5 Volt, Ground(4505M Only)FF, EFAF, AEDR,OV(4505S Only)- Full and Empty Flag (Active Low)- Almost Full, Almost Empty Flag- Input Ready, Output ValidWE2 - Write Enable Input 2RE2 - Read Enable Input 2 (Rising EdgeTriggered 3 State Control)1/16441