memory products - Al Kossow's Bitsavers

M8571S·BUS INTERFACEThe serial, 3-wire, interface (SDA, SCl and SEN,,:,ires are open drain to allow "wired-and" operation)connects several devices which can be dividedinto "masters" and "slaves". A master is a devicethat can manage a data transfer; as such, it drivesthe Start and Stop (SEN), the clock (SCl) and thedata (SDA) lines. The bus is "multimaster" in thatmore master devices can access it; arbitrationprocedures are provided in the bus management.Obviously, at least one master must be present onthe bus. The M8571 is a hardware slave device.It can only answer the requests of the masters onthe bus; therefore SDA is an 110, while SCl andSEN are inputs. The S-8US allows two operatingspeed: high (125KHz) and low (2KHz). The M8571can work at both high and low speed.START/STOP ACKNOWLEDGEThe timing specs of the S-8US protocol require thatdata on the SDA and SEN lines be stable duringthe "high" time of SCL. Two exceptions to this ruleare foreseen and they are used to signal the startand stop condition of a data transfer.A "high to loW" transition on the SEN line, with SCl"high", is a start (STA),A "low to high" transition on the SEN line, with SCl"high", is a stop.Data are transmitted in 8-bit groups; after eachgroup, a ninth bit is interposed, with the purposeof acknowledging the transmitting sequence (thetransmitter device place a "1" on the bus, the acknowledgingreceiver a "0").INTERFACE PROTOCOLThe following description deals with 8-bits datatransfers, so that it fully fits when the memory is"seen" as 128 x 8 array. Although the basic structureof the protocol remains the same the behaviourof the M8571 in 16 or 32 bit data transfers is somewhatdifferent. The differencies are descibed lateron.The interface protocol comprises:- A start condition (STA)- A "chip address" byte, trasmitted by the master,containing two different informations.a) the code identifying the device the masterwants to address (this information is presentin the first seven bits); 4bits indicates thetype of the device (Le. memory, tuning, AID,etc.; the code for memories is 1010); thenthere is a bit at low level and 2bits that arethe Chip Select configuration that mustmatch the hardware present on the 2 CSpins (this is the case of a device with 2 ChipSelect like the M8571 , for M8571 CS1 andCS2 must match respectively the 7th and the6th bit of the byte).b) the direction of transmission on the bus (thisinformation is given in the 8th bit of thebyte); "0" means "Write", that is from themaster to the slave, while "1" means"Read". The addressed slave must alwaysacknowledge.The sequence, from now on, is different accordingto the value of the RIW bit.1) RiW = "0" (WRITE)In all the following bytes the master acts astransmitter; the sequence follows with:a) a "word address" byte containing the addressof the selected memory word and/oropcode (see word address/opcode section).b) a "data" byte which will be written at the addressgiven in the previous byte.c) further data bytes which, due to the self incrementingaddress register, will be writtenin the "next" memory locations. At the endof each byte the M8571 acknowledges.d) a stop condition (STO)After receiving and acknowledging a data byte ora set of data bytes to be written, the M8571 automaticallyerases the addressed memory locationsand rewrites them with the received data. Since theEIW time for an EEPROM is in the order of 10 msthe next operation can take place only after tE~(what the master can and must do is described inthe E/W TIME SPECS section).An example of a write sequence is given beJow:o. STA1. 10100ss0 A (M8571 acknowledges only if"ss" matches its CS code)2. xyyyyyyy A3. z z z z z z z z A (at this moment the M8571starts writing zzzzzzzz at theaddress yyyyyyy)4a. t t t t t t t t H (the new data is not acknowledgedwhile the M8571 isbusy)4b. t t t t t It t A (now the M8571 writes datat t t t t t It at addressyyyyyyy + 1)The write sequence can be composed by an unlimitednumber of data bytes.7/11205