memory products - Al Kossow's Bitsavers

MK4505M/4505S(N)-25/33/50SIMULTANEOUS WRITE/READ TIMINGThe Empty Flag (EF) is guaranteed to clear (goHIGH)in response to the first rising edge of the readclock (CKR) to occur tFFL (First Flag Latency) aftera valid First Write (from the rising edge of CKw).Read clocks occurr.!!!9 less than tFFL after a FirstWrite may clear the EF, but are not guaranteed (seeFigure 10). As always, reads attempted in conjunctionwith an active Empty Flag are inhibited. Therefore,the next rising edge of CKR following tFFL willproduce the first valid read. This is the tFRL (FirstRead Latency) parameter, and must be observedfor proper system operation with the latched. EF.Coming from an empty condition, the First Readoperation should be accomplished by enablingRE1 no less than ts before the rising edge of CKRat tFRL. The a outputs will present valid data tAfrom the riSing edge of CKR.When using the MK4S0SS (Slave) separately, theuser must observe the tFRL (First Read Latency)parameter to ensure first-write-to-first-read validdata. Referring to Figure 11, the first rising edge ofCKR to occur tFRL after a First Write clock willguarantee valid data tA from the rising edge ?fCKR. Read operations attempted before tFRL ISsatisfied may result in reading RAM locations notyet written. Careful observance of tFRL by the useris a must when using free running asynchronousreadlwrite clocks on the MK4S0SS; there is no automaticread and write protection circuitry in theSlave.It should also be noted that the MK4S0SM/S hasan expected "fall-through delay time" described asFirst Write data presented to the FIFO and clockedout to the outside world. This can be calculated as:ts + tFRL + tA (from Figure 10 or 11). Further occurringvalid read clocks will present data to the aoutputs tA from the rising edge of CKR.WIDTH AND DEPTH EXPANSIONA single Master (MK4S0SM) is required for each 1kof depth configured. The number of Slaves that canbe driven by a single Master is limited only by theeffects of adding extra load capacitance (Write andRead Enable Input CapaCitance) onto th~lnputReady (DR), Output Valid (OV), Full Flag (FF) andEmpty Flag (EF) outputs. However, even 40 bits ofwidth (8 devices) results in only 40pf of loading,which corresponds to the amount of load called outin the AC Test Conditions. Additional loading willslow the flags down, but as long as Enable Set Uptime (ts) is met, slowing the flags has no negativeconsequences.WIDTH AND DEPTH EXPANSION EXAMPLESThe width and depth expansion interface timing diagrams(Figures 13 and 14) are in reference to thewidth and depth expansion schematic in Figure 12(For simplicity all clocks have the same frequencyand transistion rate). Example 1 - First Write SinceEmpty - Reading the timing diagram from the topleft to bottom right, one can determine that Figure13 illustrates the effects of the first WRITE/READ9!9les from an EMPTY I!!:.@Y .Q!.,FIFOs. Both of theEF pins are initially low (EFx, EF and RE~. As datais written into Bank A, the expansion clock readsdata from Bank A and writes it to Bank B, the interfaceEF (EF and RE 2) and the external EF (EFx)go inactive (logic 1) while data is shifted throughthe FIFO array from BankAthrough Bank B to theexternal output (ax). The EF logic goes valid (logic0) once data is shifted out of its respective bank.Example 2 - First Read Since Full - Reading the timingdiagram from the bottom left to top right, onecan determine that Figure 14 illustrates the effectsof the first READs from a FULL array of FIFOs. Asdata is read out of the system (ax), it allows BankB to receive data shifted from Bank A. As Bank Bshifts data out via ax, allowing Bank A to shift datainto Bank B, both banks will show a reset FF status(logic 1) on the eX.Q!!nsion FF (FF and WE~ a~ wellas the external FF (FFx). When Bank A IS nolonger considered FULL, Data In from the system(Ox) is now written into Bank A and shifted to BankB until the FIFO array is again completely Full.APPLICATIONThe MK4S0S operates from a S.O volt supply. It iscompatible with aU standard TTL families on all inputsand outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TTL devices. Additionally, becausethe outputs can drive rail-to-rail into high impedanceloads, the MK4S0S can also interface to S voltCMOS on all inputs and outputs.Since very high frequency current transients will beassociated with the operation of theMK4S0S, powerline inductance must be minimized on the circuitboard power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance. A high frequencydecoLipling capacitor should be placed nextto each FIFO .. The capacitor should be 0.1 "F or larger.Also, a pull-up resistor in the range of 1K ohmsis recommended for the RESET input pin to improveproper operation.Though often times not thought of as such, thetraces on a memory board are basically unterminated,low impedance transmission lines. As suchthey are subject to signal reflect~ons .ma.nifested.asnoise, undershoots and excessive rlngmg. Seriestermination in close proximity to the TTL drivers canimprove driver/signal path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.101164S0