memory products - Al Kossow's Bitsavers

MK48C02A/12A(K,N)-15/20/25WRITE MODEThe MK48C02A112A is in Write Mode whenever theWand E inputs are held low. The start of a Writeis refe~nee!!. to the latter occurring falling edge ofeither W or E.~ Wme is terminated by the earlierrising edge of W or E. The .l!9dr~ses must be heldvalid throughout the cycle. W or E must return. high,for a minimum of tWR prior to the initiation ofanother Read or Write Cycle. Data-in must be validfor tos prior to the End of Write and remain validfor tOH afterward.Some processors thrash producing spurious WriteCycles during power-up, despite !!ppli~tion of apower-on reset. Users should force W or E high duringpower-up to protect memory after Vee reachesVee (min) but before the processor stablizes.The MK48C02~12A G input is a DON'T CARE inthe write mode. G can be tied low and two-wire RAMcontrol can be implemented. A low on W will disablethe outputs tWEZ after W falls. Take care toavoid bus contention when operating with two-wirecontrol.FIGURE 4. WRITE-WRITE-READ TIMINGWRITEWRITEREADwVALIDINVALIDINVALIDOUTAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE TIMING)(O°C:s;TA:s;70°C) (Vee (Max)2:Vec2:Vec (Min))MK4BCX2A·15 MK4BCX2A·2D MK4BCX2A·25SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 150 200 250 nstAS Address Setup Time 0 0 0 nstAW Address Valid to End of Write 120 140 180 nstCEw Chip Enable to End of Write 90 120 160 nstWEW Write Enable to End of Write 90 120 160 nstWR Write Recovery Time 10 10 10 nst DS Data Setup Time 40 60 100 nstOH Data Hold Time 0 0 0 nstWEZ Write Enable Low to High-Z 50 60 80 ns4/10292