memory products - Al Kossow's Bitsavers

MK4511(N,K)-12115/20WRITE MODEThe MK4511 is in Write. Mode whenever Write Enable(WE) and Chip Enable (CE) are active low. Asin Read Mode, the falling edge of CElatches theaddresses present at the AD lines. The same addressesset-up and hold times apply. Input to theAD pins must then change from the address to inputdata. Input data present on the AD lines mustbe stable for tosprior to the end of write and mustremain valid for tOH afterward. A writ~le may beended by the riSing edge of WE or CEo Chip Enablerecovery time must also be observed in writemode.Even if WE becomes active prior to CE becomingactive, CE falling actually begins the cycle, latchingthe address present on the AD lines. Such cyclesmust reference t~, tos and 10H to the riSingand falling. edges of CE and WE.Read-Modify-Write cycles are possible if the outputsare enabled and the assertion of WE is dela~through tea: The write cyQle will begin when WEgoes low. WE going low or OE going high will retumthe output drivers to high-Z within tWEz..2! toEZrespectively. The address latched when CE wentlow is still the valid address as the write cycle proceeds.Th!.9'Cle is ended by the earlier rising edgeofCE or WE.FIGURE 4. WRITE-WRITE-READ MODIFY WRITEWRITEWRITEREAD MODIFY WRITEADI ..I~ ft=-I~~WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°CsT As70"C) (Vee = 5.0 V ± 10 percent)MK4511-12 MK4511-15 MK4511-20SYM PARAMETERS MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 150 190 250 nsteEW Chip Enable to End of Write 120 150 200 nstWEW Write Enable to End of Write 80 105 130 nstos Data Setup. Time 40 55 65 nstOH Data Hold Time 10 10 10 ns4111432