memory products - Al Kossow's Bitsavers

MK41H80(N,P)-20/25/35FLASH CLEAR CYCLEA Flash Clear Cycle begins as CCR is brought low(see Figure 5). A Flash Clear sets all 16,384 bits inthe RAM to logic zero. Control Inputs will not berecognized from n after CLR falls to teR after CCRis brought high. OE and WE are Don't Cares andDO is High-Z. MAlCH will be invalid while CLR is low.AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(OOCsT As70OC) ('Icc = 5JN ±100Al)·20 ·25 ·35SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStFCC Flash Clear Cycle Time 40 50 70 nslex Clear (CLR) to Inputs Don't Care 0 0 0 nsteR End of Clear (CLR) to Inputs 0 0 0 nsRecognizedteLP Flash Clear (C[R) Pulse Width 36 44 60 nsFigure 5, Read-Flash Clear-Write CycleREAD CYCLE CLEAR CYCLE WRITE CYCLE14---- e ----I~f---- tFee--_~---le ----I~ADDRADDRESS ADDRESS ~XXX~ ADDRESS___..II\.__......::VA:::L:::ID:"""_-'I\...,!!VA:::L:::ID'.....,J r\MXXlVALID00'II IDEA:}leLPI~...!......!....I __I.--I Aw_I leR j.---'" I--- ... _ Lf-r-· ----J-+l .-- -I IDS j.---___ -.:..~_I_.A__ VALID £: