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Part-I - Controller General of Patents Designs and Trademarks

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(12) PATENT APPLICATION PUBLICATION (21) Application No.1636/CHE/2012 A<br />

(19) INDIA<br />

(22) Date <strong>of</strong> filing <strong>of</strong> Application :25/04/2012 (43) Publication Date : 21/06/2013<br />

(54) Title <strong>of</strong> the invention : NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF<br />

MANUFACTURING THE SAME<br />

(51) International classification<br />

:H01L (71)Name <strong>of</strong> Applicant :<br />

33/00 1)NICHIA CORPORATION<br />

(31) Priority Document No<br />

:2011- Address <strong>of</strong> Applicant :491-100, OKA, KAMINAKA-CHO,<br />

098851 ANAN-SHI, TOKUSHIMA 774-8601 Japan<br />

(32) Priority Date :27/04/2011 (72)Name <strong>of</strong> Inventor :<br />

(33) Name <strong>of</strong> priority country :Japan 1)YONEDA, AKINORI<br />

(86) International Application No<br />

Filing Date<br />

:NA<br />

:NA<br />

2)KAWAGUCHI, HIROFUMI<br />

3)DEGUCHI, KOUICHIROH<br />

(87) International Publication No : NA<br />

(61) Patent <strong>of</strong> Addition to Application Number<br />

Filing Date<br />

:NA<br />

:NA<br />

(62) Divisional to Application Number<br />

Filing Date<br />

:NA<br />

:NA<br />

(57) Abstract :<br />

To provide a reliable nitride semiconductor light emitting element having a thick metal bump <strong>and</strong> a method <strong>of</strong> manufacturing the<br />

nitride semiconductor light emitting element with an improved productivity, the manufacturing method <strong>of</strong> a flip-chip nitride<br />

semiconductor light emitting element including: a nitride semiconductor light emitting element structure having an n-type nitride<br />

semiconductor layer <strong>and</strong> a p-type nitride semiconductor layer, which are laminated on a substrate, <strong>and</strong> an n-side electrode<br />

connecting surface for connecting an n-side electrode to the n-type nitride semiconductor layer <strong>and</strong> a p-side electrode connecting<br />

surface for connecting a p-side electrode to the p-type nitride semiconductor layer on the same plane side <strong>of</strong> the substrate, the n-<br />

side electrode being connected to the n-side electrode connecting surface <strong>and</strong> the p-side electrode being connected to the p-side<br />

electrode connecting surface; <strong>and</strong> metal bumps formed on the n-side electrode <strong>and</strong> the p-side electrode, wherein a protective layer<br />

forming step, a first resist pattern forming step, a protective layer etching step, a first metal layer forming step, a second resist<br />

pattern forming step, a second metal layer forming step <strong>and</strong> a resist pattern removing step are sequentially performed.<br />

No. <strong>of</strong> Pages : 171 No. <strong>of</strong> Claims : 13<br />

The Patent Office Journal 21/06/2013 13951

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