Ion Implantation and Synthesis of Materials - Studium

14 Application of Ion Implantation Techniquesin CMOS FabricationContributed by Lin Shao, Los Alamos National Laboratory14.1 IntroductionThis chapter deals with ion implantation in complementary metal oxidesemiconductor (CMOS) fabrications. CMOS has become the dominant MOStechnology since its invention in the 1960s. The number of transistors integratedon a die tends to double every 14–18 months. This is known as Moore’s Law. Thisrequires a continuous reduction in the size of CMOS devices. Given that there isgreater complexity in fabricating n- and p-channel CMOS devices relative to otherdevices, reducing the size of CMOS devices faces fundamental physicallimitations, such as short-channel effects and hot-electron effects. These issueswill be discussed later in this chapter. Some of these complexity-derivedlimitations have been alleviated by the use of ion implantation, which is wellsuited for current integration processes.14.2 Issues During Device ScalingTo maintain a proper device function during device size scaling, the thresholdvoltage, V T , must not change significantly. The threshold voltage is defined as thevalue of the gate voltage needed to induce a conducting channel under the gateoxide. The threshold voltage is given byV = V + V + V + V (14.1)T ms ox d iwhere V ms is the work function difference between the gate and the Si substrate.The work function of a material is the minimum amount of work required to movean electron from its Fermi level to the vacuum level. V ox denotes the fixed chargeat the oxide–silicon interface. V d is due to the charge in the depletion region, andV i is the voltage needed to invert the surface. A major component that contributesto the threshold voltage is V d , which can be expressed as193