Ion Implantation and Synthesis of Materials - Studium

198 14 Application of Ion Implantation Techniques in CMOS FabricationGate oxideGate(a)SourceDrainp+ +p++-+GateSourceDrainp+ + - +-p+(b)L effFig. 14.4. Schematic illustration of hot-electron effects (a) avalanche multiplication in thechannel and (b) hot-electron-induced channel shortening14.2.3 LatchupCMOS devices can develop a serious problem called latchup, in which junctionsin different devices connect and form a forward-biased diode structure, leading toa catastrophic current which destroys the circuit. As illustrated in Fig. 14.5a, thelatchup is caused by the formation of a pnpn device between the terminal of VSSand VDD (see Chap. 9, Sect. 1.3). In a latchup condition, the pnpn device isbiased such that the collector current of the pnp bipolar transistor supplies a basecurrent to the npn bipolar transistor in a positive feedback situation. The latchupcan cause device function failure or even self-burnout. Figure 14.5b shows thebipolar components and resistive components of a latchup configuration. Theconduction state of a pnp device requires V E < V B V B >> V C , where V E , V B , and V C are electricpotentials of the emitter (E), the base (B), and the collector (C) (see Chap. 9,Sect. 1.1). In both cases, the devices will be turned “off” if V B ~ V E or V B ~ V C .Therefore, the latchup can be minimized by making the resistances of R S and R Win Fig. 14.5b as small as possible, or by physically separating the base from thecollector of the two transistors. In Sect. 14.3, we will discuss how ion implantationis used in CMOS fabrication to form retrograde wells for the purpose of reducinglatchup.