Ion Implantation and Synthesis of Materials - Studium

194 14 Application of Ion Implantation Techniques in CMOS FabricationV Q C (14.2)d= B /oxwhere C ox is the oxide capacitance per unit area, and Q B is bulk charge, which iscontrolled by the gate. One basic model to estimate the effect of device scaling onthe change in V T was given by Yau (1974). Figure 14.1a–c shows a threedimensionalsketch of a NMOSFET with its cross-section views. The key in Yau’smodel is the introduction of a trapezoidal region representing the gate-controlledcharge. The charge beyond that region (shaded area) is controlled by the sourceand drain. By subtracting the shaded triangular region from the rectangular region,the charge controlled by the gate is given byQB= area(EFHG) − 2 × area(AGH)⎛cB WLW c 2 ∆LW⎞= qN ⎜ − W2⎟(14.3)⎝⎠where q is the electric charge, N B is the channel doping concentration, W is thewidth of the device, and L is the gate length. The model has assumed that source,drain, and gate have the same depletion width, W c . The value of ∆L in (14.3) canbe obtained by using a triangle encompassed by ABC, as shown in Fig. 14.2c.Hence2 2 2c c( ∆ L + r) + W = ( W + r )(14.4)where r is a radius of curvature, which describes the lateral and vertical depth ofsource and drain junctions. Combining the above equations allows Q B to beexpressed as⎧1/2⎪ ⎡⎛2Wc⎞ ⎤ r ⎫⎪QB= qNBWLWc⎨1 − ⎢⎜1 + ⎟ − 1⎥⎬(14.5)⎪⎩⎢⎣⎝r ⎠ ⎥⎦L⎭⎪Equation (14.5) describes the total depletion charge in the channel that isterminated on the gate. It should be noted that the gate length, L, in (14.3) and(14.5) is the effective gate length, which has taken into the account the lateraldopant diffusion of source and drain junctions under the gate. L is less than thephysical gate length, as shown in Fig. 14.1b.One important conclusion resulting from (14.5) is that the threshold voltagedepends not so much on the actual value of r, but on the ratio of r to the gatelength, L. The requirement that the depth of the source and drain junctions shouldbe scaled linearly with the gate length is one important rule guiding devicescaling. The physical gate length of MOSFET has been reduced from 10 µm in the1970s to a present day size of sub-100 nm. Correspondingly, the depths of sourceand drain junctions have been reduced from a few microns to sub-100 nm.