ModuleWare Reference Guide - Hornad

Arithmetic PartsAccumulator (acc)adder or a subtractor is used, do not synthesize this part separately and use flatten for theinstance of this part.If input ports clk and rst (for asynchronous behavior) are not enabled, the output ports of theflip-flops retain their values.This part is equivalent to a n-bit adder_subtractor, an n-bit multiplexer and an n-bit register;where n is the width of the ports din and dout. The hardware cost depends upon the usage ofspecific scalar input ports. The implementation can be controlled via the synthesis script.If clk_en is not connected, it is driven by 1. If the clock enable feature is not used, the portclk_en must be unconnected and the parameter clk_en_type must be set to ActiveHigh. Portclk_en can also be driven by an active driver, in which case the clk_en_type must be correctlyadjusted. The HDL code for clk_en is optimized away if it is not used.If port cin is unconnected, it is driven by 0.FunctionAn enabled clk trigger is a trigger that occurs when input port clk_en is active.If rst is synchronous, then at every enabled clk trigger (rising edge if clk_type = Rising; fallingedge if clk_type = Falling):dout= rst_val= din= dout + din + cin= dout - din - cinif rst is active, elseif load is active, elseif additionotherwiseIf rst is asynchronous:dout= rst_val= din= dout + din + cin= dout - din - cinif rst is active (irrespective of the clk trigger),else at every enabled clk trigger (rising edge ifclk_type = Rising; falling edge if clk_type = Falling):if load is active, elseif additionotherwiseTruth TableAsynchronous high rst and positive polarities (for negative polarities invert the values)Table 6-5. Accumulator Truth Table — Asynchronous high rst, PositivePolaritiesclk rst load addsub clk_en creg- 1 - - - rst_val- 0 - - 0 cregPosedge 0 1 - 1 dinPosedge 0 0 1 1 creg+din+cin104ModuleWare Reference Manual, Library Version 1.9September 18, 2008