ModuleWare Reference Guide - Hornad

Optional PortsIntroductionOptional PortsOptional ports are listed in the ModuleWare Parameters dialog box. The HDL for these ports isoptimized away when the HDL is generated. You can explicitly remove optional scalar ports bysetting the _type parameter to None. Optional vector ports may have an enumerated_type parameter (Enabled, Disabled) which can be set to Disabled.Reset BehaviorReset functionality is available on all of the Sequential parts that use the rst input port. A partcan be reset asynchronously or synchronously. A part can be reset with a value of 1 or 0 on therst port. This behavior of the rst port is controlled by the parameter rst_type.• For all parts with a rst port with the exception of the Bank of Latches (latch), rst_type isenumerated with the values SyncActiveHigh, AsyncActiveHigh, SyncActiveLow andAsyncActiveLow.• If the value of rst_type is SyncActiveHigh, the part gets reset synchronously when thevalue of input port rst is 1.• If the value of rst_type is AsyncActiveHigh, the part gets reset asynchronously when thevalue of input port rst is 1.• If the value of rst_type is SyncActiveLow, the part gets reset synchronously when thevalue of input port rst is 0.• If the value of rst_type is AsyncActiveLow, the part gets reset asynchronously when thevalue of input port rst is 0.• If the reset is asynchronous (rst_type has either the value AsyncActiveHigh or the valueAsyncActiveLow), the scalar input port rst has a priority higher than the clock port(clk).• The rst port is not affected by scalar input port clk_en if rst_type is asynchronous.• If the reset is synchronous (rst_type is SyncActiveHigh or SyncActiveLow), the scalarinput port rst has a priority lower than the clock port (clk).• Scalar input port clk_en indirectly deactivates the rst port if rst_type is synchronous.• The parameter rst_type for the Bank of Latches (latch) part is enumerated with valuesActiveHigh (positive polarity) and ActiveLow (negative polarity).The polarity indication ( or no ) for a rst port on a block diagram is dynamically set by theparameter rst_type. If the value is set to SyncActiveLow or AsyncActiveLow, a inverted signalindicator appears on the port. If the value is set to SyncActiveHigh or AsyncActiveHigh, theindicator disappears.ModuleWare Reference Manual, Library Version 1.9 19September 18, 2008