ModuleWare Reference Guide - Hornad

IntroductionNaming ConventionsNaming ConventionsModuleWare parts use the following conventions for port naming and location:• Data input ports for logical parts usually start with din.• The data output ports for logical parts usually start with dout.• The control (enable/disable) ports for tristates and memory parts include the string enain their names.• The clock port is named clk.• The clock polarity is controlled by enumerated parameter clk_type which can have thevalues (Rising, Falling) for Verilog or (Rising, Falling, RisingLast, FallingLast,RisingEdge, FallingEdge) for VHDL.• The clock enable port (gated clock) is named clk_en.• The polarity of input port clk_en is controlled by enumerated parameter clk_en_type(ActiveHigh, ActiveLow).• The reset port is named rst.• The rst port is controlled by enumerated parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).• The set port is named set.• The set port is controlled by enumerated parameter set_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).• The clear port is named clr.• The clr port is controlled by enumerated parameter clr_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).• The preset port is named pre.• The pre port is controlled by enumerated parameter pre_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).• The enable port is named enable.• The enable port is controlled by enumerated parameter enable_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).• The load port is named load.• The load port is controlled by enumerated parameter load_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).• The gate port is named gate.16ModuleWare Reference Manual, Library Version 1.9September 18, 2008