ModuleWare Reference Guide - Hornad

Synthesizable Dual-Port RAM (ramdp)Memory PartsSynthesizable Dual-Port RAM (ramdp)This part implements a synthesizable dual-port Random AccessMemory (RAM) which will infer a FIFO style dual port RAMwith separate read din and write dout data ports synchronizedto separate clocksThis part has independent input and output synchronous ports.The size of the RAM is specified by the address_width anddata_width parameters.The width of address ports rdaddr and wraddr must be equalto the address_width parameter.However, if the address_width parameter is empty, then thesize of the RAM is determined from the width of the rdaddr orwraddr ports.The width of input port din must be equal to or greater than the data_width parameter. If thedata_width parameter is empty, then the size of the RAM is determined from the width of thedin port.The RAM can be initialized using the initial_value parameter which must be a valid LNBFstring. All locations in the RAM will have the same initial value defined by the initial_valueparameter.The RAM has write and read operations. A write operation takes place if wrclk goes high andthe optional scalar input port we is enabled (we = 1). A read operation takes place if rdclk goeshigh and the optional scalar input port re is enabled (re = 1). If the optional re and we ports arenot used the write and read operations are controlled by solely the wrclk and rdclk ports.In a write operation, the value of the input bus din is written to the address location specified bythe value of the input bus wraddr. In a read operation, the value in the address locationspecified by rdaddr is placed on the output port dout.The enumerated parameters wrclk_type and rdclk_type (Rising, Falling, RisingLast,FallingLast, RisingEdge, FallingEdge) and we_type (ActiveHigh, ActiveLow) control whichclock edge is used for the read and write operations.(Note that RisingLast, FallingLast, RisingEdge and FallingEdge are supported for VHDL only.)This part can be synthesized using Altera or Xilinx technologies.ModuleWare Reference Manual, Library Version 1.9 225September 18, 2008