ModuleWare Reference Guide - Hornad

Memory PartsSynthesizable Dual-Port RAM (ramdp)ParametersTable 9-11. Synthesizable Dual-Port RAM ParametersParameter Values Defaultdin, doutrdaddr, wraddrrdclk_typere_typewe_typewrclk_typeaddress_widthdata_widthinitial_valuePort widths (must be > 0)Port widths (must be > 0)Rising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh, ActiveLowActiveHigh, ActiveLowRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeWidth of the addressable memoryWidth of the RAM dataInitial value of RAMAutomaticAutomaticRisingActiveHighActiveHighRising380Design Rule Checks• An error is issued if the width of any port cannot be determined, if any of ports rdclk,wrclk, re and we do not have a fixed width of 1, if ports din and dout do not have the samewidth, if the width of ports rdaddr or wraddr do not equal the value of the address_widthparameter or if the width of input port din is less than the data_width parameter.• A warning is issued and HDL generation fails for this part if any of ports din, dout, rdaddr,wraddr, rdclk or wrclk are not connected.• A warning is issued and generation continues if the width of input port din is greater thanthe data_width parameter.226ModuleWare Reference Manual, Library Version 1.9September 18, 2008