ModuleWare Reference Guide - Hornad

Register PartsRS Flip-Flop (rsff)Table 7-21. RS Flip-Flop Truth Table — Synchronous rst and set (cont.)enable clk rst set q qb- posedge 1 0 / NC rst_val NOT(rst_val)- posedge 0 / NC 1 set_val NOT(set_val)NC posedge 0 / NC 0 / NC RS TT NOT(RS TT)0 posedge 0 / NC 0 / NC q qb1 posedge 0 / NC 0 / NC RS TT NOT(RS TT)ParametersTable 7-22. RS Flip-Flop ParametersParameter Values Defaultq, qb Port widths (must be > 0) Automaticclk_typeenable_typeqb_typer_typerst_types_typeset_typeinitializationrs_priorityrst_valset_valRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh,ActiveLow,NoneEnabled,DisabledActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledR-S,S-RRegister reset value (must be >= 0)Register set value (must be >= 0)RisingActiveHighEnabledActiveHighAsyncActiveHighActiveHighAsyncActiveHighDisabledR-S01Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, enable, rst,set, r and s do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports r, s and clk are notconnected or if at least one of ports q and qb are not connected.156ModuleWare Reference Manual, Library Version 1.9September 18, 2008