ModuleWare Reference Guide - Hornad

Memory PartsStack (stack)ParametersTable 9-10. Stack ParametersParameter Values Defaultsin, sout Port widths (must be > 0) Automaticclk_en_typeclk_typeempty_typefull_typepop_typepush_typerst_typestack_sizeActiveHigh,ActiveLowRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh,ActiveLowActiveHigh,ActiveLowActiveHigh,ActiveLowActiveHigh,ActiveLowSyncActiveHigh,AsyncActiveHigh,SyncActiveLow,AsyncActiveLowSize of the FIFO (maximum number of data elements)ActiveHighRisingActiveHighActiveHighActiveHighActiveHighAsyncActiveHigh1Design Rule Checks• An error is issued if the width of any port cannot be determined or if any of ports clk,clk_en, rst, pop, push, full and empty do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports rst, push, pop, sin,clk or sout are not connected.224ModuleWare Reference Manual, Library Version 1.9September 18, 2008