ModuleWare Reference Guide - Hornad

Stack (stack)Memory PartsStack (stack)This part implements a stack. Data can be loaded (pushed) into theinternal registers and read (popped) at a later time. All operations inthis part (except for reset) are synchronous with respect to the clock.The depth is controlled by the parameter stack_size. The stacksupports two input/output operations.A push operation takes the value of the input port sin and places it inthe internal registers.A pop operation takes the newest value in the internal registers andplaces it in the output port sout. This value is retained on sout, untilthe next pop operation.The pop operation is controlled by the scalar input port pop. Thepush operation is controlled by the scalar input port push and hasprecedence over the pop operation.The polarity of the scalar input port pop is controlled by the enumerated parameter pop_type(ActiveHigh, ActiveLow). The polarity of the scalar output port push is controlled by theenumerated parameter push_type (ActiveHigh, ActiveLow).The part consists of the required number of the internal registers, an address counter and thecontrol logic. The address counter keeps count of the current address. This value is used todisable the pop and push operations. This counter decides whether the stack is empty (counter =0) or full (counter = stack_size). The reset operation is required before a correct operation of thestack (for post synthesis simulation match). Pop operations cannot be done before a pushoperation.Push operations are disabled if the internal registers are full (address counter = stack_size). Popoperations are disabled in the internal registers are empty (address counter = 0). If the internalregisters are full and both push and pop operations are triggered, the pop operation takes place.Only when the internal registers are full does the pop operation takes precedence over the push(because write is disabled). Scalar output port full is activated if the internal registers are full.Scalar output port empty is activated if the internal registers are empty. The polarity of thescalar output port full is controlled by the enumerated parameter full_type (ActiveHigh,ActiveLow). The polarity of the scalar output port empty is controlled by the enumeratedparameter empty_type (ActiveHigh, ActiveLow).The part can be triggered on either the rising or falling edge of the scalar input port clk. Thepolarity of clk is controlled by the enumerated parameter clk_type (Rising, Falling, RisingLast,FallingLast, RisingEdge, FallingEdge).(Note that RisingLast, FallingLast, RisingEdge and FallingEdge are supported for VHDL only.)The clk can optionally be enabled by the scalar input port clk_en. The polarity of clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not changethe value of the parameter clk_en_type, if the clk_en port is not used.ModuleWare Reference Manual, Library Version 1.9 221September 18, 2008