ModuleWare Reference Guide - Hornad

ParametersRegister PartsJK Flip-Flop (jkff)Table 7-11. JK Flip-Flop Truth Table — Synchronous clr and pre (cont.)enable clk clr pre q qb- posedge 1 0 / NC clr_val NOT(clr_val)- posedge 0 / NC 1 pre_val NOT(pre_val)NC posedge 0 / NC 0 / NC JK TT NOT(JK TT)0 posedge 0 / NC 0 / NC q qb1 posedge 0 / NC 0 / NC JK TT NOT(JK TT)Table 7-12. JK Flip-Flop ParametersParameter Values Defaultq, qb Port widths (must be > 0) Automaticclk_typeclr_typeenable_typej_typek_typepre_typeqb_typeclr_valinitializationpre_valRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneActiveHigh,ActiveLow,NoneActiveHigh,ActiveLowActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledRegister clear value (must be >= 0)Enabled,DisabledRegister preset value (must be >= 0)RisingAsyncActiveHighActiveHighActiveHighActiveHighAsyncActiveHighEnabled0Disabled1Design Rule Checks• An error is issued if the width of any port cannot be determined, if ports clk, clr, enable andpre do not have a fixed width of 1or if ports j, kq and qb do not have the same width.• A warning is issued and HDL generation fails for this part if any of ports j, k and clk are notconnected or if at least one of ports q and qb are not connected.ModuleWare Reference Manual, Library Version 1.9 149September 18, 2008