ModuleWare Reference Guide - Hornad

Sequential PartsConfigurable Counter (cntr)Configurable Counter (cntr)This part provides a highly configurable and highly parameterizedcounter functionality.When the scalar input port clk is triggered, the counter is activatedand the new value if placed in the output port count. The maxcntrpart has been obsoleted and the configurable counter in binary modegives the same functionality. A value of 1 is placed in the scalaroutput port max if the maximum value is reached.Dynamic control is provided to increment or decrement the counterduring the counter operation. A new value can be loaded into thecounter.This part provides four modes for counting: Binary, Johnson, LinearFeedback Shift Register and One-hot controlled by the enumerated parameter style (Binary,Johnson, LFSR, Onehot).The part can be triggered on the rising edge or the falling edge of the scalar input port clk. Thepolarity of port clk is controlled by the enumerated parameter clk_type (Rising, Falling). Notethat RisingLast, FallingLast, RisingEdge and FallingEdge are also supported for VHDL.The clk can optionally be enabled by the scalar input port clk_en. The polarity of port clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not changethe value of the parameter clk_en_type if the clk_en port is not used.The counter can be reset to the value of the parameter rst_val by activating the scalar input portrst. If the style is LFSR, the actual reset value is derived. The reset mode is controlled by theenumerated parameter rst_type (SyncActiveHigh, AsyncActiveHigh, SyncActiveLow,AsyncActiveLow).The value of the input data bus port din is loaded into the counter if the scalar input port load isactive. The scalar input port rst has a priority over port load. If the rst port is active, no valuecan be loaded.The load mode is controlled by the enumerated parameter load_type (ActiveHigh, ActiveLow).If load_type = ActiveHigh, the load port is activated with a value of 1. If port load isunconnected, it is driven by 0 (disabled). The values are reversed if load_type = ActiveLow.This part is equivalent to an n bit counter; where n is the width of the ports din and count. Theimplementation can be controlled by the synthesis scripts. This part is very heavilyparameterized and the performance is affected by the configuration of the counter.If clk_en is not connected, it is driven by 1. If the clock enable feature is not used, the scalarinput port clk_en must be unconnected and the parameter clk_en_type must be set toActiveHigh. Port clk_en can also be driven by an active driver, in which case the clk_en_typemust be correctly adjusted. The HDL code for clk_en is optimized away if it is not used.If the enumerated parameter up_dn_type (ControlledByPort, Up, Down) is set toControlledByPort, the direction of the counter is controlled by the scalar input port up_dn. Ifthe value of the port is 1 (or the parameter is set to Up), the count is upwards on an enabled178ModuleWare Reference Manual, Library Version 1.9September 18, 2008