ModuleWare Reference Guide - Hornad

Memory PartsRegister File (regfile)Register File (regfile)This part implements a Register File (RAM based). This part isuseful in processor designs. The depth of the RAM is given by theparameter regfile_size. The internal memory elements have alatch behavior (that is, they are level sensitive).The Register File provides two read and one write operations.These operations can be done simultaneously. The writeoperations takes place if the scalar input port wena is enabled(wena = 1). The read operations takes place if the scalar inputports rena0 or rena1 are enabled (rena0 = 1 or rena1 = 1).In a write operation, the value of the input bus din is written to theaddress location specified by the value of the input bus waddr.Ina read operation controlled by the scalar input port rena0, thevalue in the address location (specified by the value of the inputbus raddr0) is placed in the output port dout0.In a read operation controlled by the scalar input port rena1, the value in the address location(provided by the value of the input bus port raddr1) is placed in the output port dout1. If theread operation is disabled by the scalar input port rena0, the output port dout0 goes to tristate.If the read operation is disabled by the scalar input port rena1, the output port dout1 goes totristate. While the read and write operations can be done simultaneously, you should not enableboth read and write operations on the same address location at the same time. An internalregister file table is maintained. When write operations are not taking place, this table maintainsits value.If the value of the address port raddr0 is greater than the value of the parameter regfile_size, thescalar output port raddr0_error is set to 1. In these cases, read operations do not take place viathe address port raddr0. If the value of the address port raddr1 is greater than the value of theparameter regfile_size, the scalar output port raddr1_error is set to 1. In these cases, readoperations do not take place via the address port raddr1. If the value of the address port waddris greater than the value of the parameter regfile_size (the size of the RAM table), the scalaroutput port waddr_error is set to 1. In these cases, write operations do not take place via theaddress port waddr. The Register File operations are disabled if the addresses are out of range.The part does not have timing control. Users are responsible for the timing control and forverifying that the values on the input ports are retained for sufficient time. You are advised toimplement a good sequential memory controller for this part to work in a sequential design. Donot synthesize this part. Memory compilers perform better than synthesis on such parts.This is a non-synthesizable part. Even though synthesis tools can accept the code generated forthis part, do not synthesize this part.214ModuleWare Reference Manual, Library Version 1.9September 18, 2008