ModuleWare Reference Guide - Hornad

Register PartsJK Latch (jklatch)Synchronous clr and pre and asynchronous enable:Table 7-17. JK Latch Truth Table — Synchronous clr and pre, Asynchronousenableenable gate clr pre q qb- - 1 - / NC q qb- - 0 / NC 1 q qb1 / NC 1 1 0 / NC clr_val NOT(clr_val)1 / NC 1 0 / NC 1 pre_val NOT(pre_val)NC 1 0 / NC 0 / NC JK TT NOT(JK TT)0 1 0 / NC 0 / NC q qb1 1 0 / NC 0 / NC JK TT NOT(JK TT)ParametersTable 7-18. JK Latch ParametersParameter Values Defaultq, qb Port widths (must be > 0) Automaticclr_typeenable_typegate_typej_typek_typepre_typeqb_typeclr_valinitializationpre_valAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneActiveHigh,ActiveLowActiveHigh,ActiveLowActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledRegister clear value (must be >= 0)Enabled,DisabledRegister preset value (must be >= 0)AsyncActiveHighSyncActiveHighActiveHighActiveHighActiveHighAsyncActiveHighEnabled0Disabled1Design Rule Checks• An error is issued if the width of any port cannot be determined, if ports gate, clr, enableand pre do not have a fixed width of 1 or if ports j, kq and qb do not have the same width.• A warning is issued and HDL generation fails for this part if any of ports j, k and gate arenot connected or if at least one of ports q and qb are not connected.ModuleWare Reference Manual, Library Version 1.9 153September 18, 2008