ModuleWare Reference Guide - Hornad

Sequential PartsBank of Flip-Flops (dff)Bank of Flip-Flops (dff)This part provides a bank of D-type flip-flops (registers). When the scalarinput port clk is triggered, the data from input port din is shifted into theoutput port q. The output port qb has the bitwise inverted value of outputport q.The part can be triggered on the rising edge or the falling edge of thescalar input port clk. The polarity of the scalar input port clk is controlledby the enumerated parameter clk_type (Rising, Falling). Note thatRisingLast, FallingLast, RisingEdge and FallingEdge are also supportedfor VHDL.The clk can optionally be enabled by the scalar input port clk_en. The polarity of port clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not changethe value of clk_en_type if the clk_en port is not used.The register can be reset to the value of the parameter rst_val by activating the scalar input portrst. The mode of the rst is controlled by the enumerated parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow). If input ports clk and rst (forasynchronous behavior) are not enabled, the output ports of the flip-flops retain their values.This part is equivalent to n flip-flops where n is the width of the ports din, q and qb.The inferred register depends upon the type of reset behavior. The gate count changessignificantly if the synthesis tool is able to pick up smaller flip-flops. Note that using qb doesnot imply extra inverters; these inverters are usually absorbed by inferred flip-flops becausemost have a qb port.If clk_en is not connected, it is driven by 1. If the clock enable feature is not used, the scalarinput port clk_en must be unconnected and the parameter clk_en_type must be set toActiveHigh. Port clk_en can also be driven by an active driver, in which case the clk_en_typemust be correctly adjusted.The HDL code for unconnected optional ports is optimized away.Parameter rst_val can take LNBF format as described in the Constant Value (constval) model,with no limitation on the size of the q and qb ports.FunctionAn enabled clk trigger is a trigger that occurs when input port clk_en is active.If rst is synchronous then at every enabled clk trigger (rising edge if clk_type = Rising; fallingedge if clk_type = Falling):qqb= rst_val= din= NOT(rst_val)= NOT(din)if rst is activeotherwiseif rst is activeotherwise170ModuleWare Reference Manual, Library Version 1.9September 18, 2008