ModuleWare Reference Guide - Hornad

Sequential PartsThree-state Bank of Flip-Flops (triff)This table is for synchronous high reset.Table 8-40. Three-State Bank of Flip-Flops Truth Table —Synchronous High Resetclk_en clk rst creg0 - - creg1 posedge 1 rst_val1 posedge 0 dinParametersTable 8-41. Three-State Bank of Flip-Flops Truth Table —Synchronous High Resetoena q qb0 ‘Z...’ ‘Z...’1 creg NOT(creg)Table 8-42. Three-State Bank of Flip-Flops ParametersParameter Values Defaultdin, q, qb Port widths (must be > 0) Automaticclk_en_typeclk_typeoena_typeqb_typerst_typerst_valActiveHigh,ActiveLowRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh,ActiveLowEnabled,DisabledSyncActiveHigh,AsyncActiveHigh,SyncActiveLow,AsyncActiveLowRegister reset value (must be >= 0)ActiveHighRisingActiveHighEnabledAsyncActiveHigh0Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, clk_en, oenaand rst do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports din, clk, oena orrst are not connected or if at least one of the ports q or qb are not connected.204ModuleWare Reference Manual, Library Version 1.9September 18, 2008