ModuleWare Reference Guide - Hornad

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Memory PartsSingle Port RAM (ram)Single Port RAM (ram)This part implements a Random Access Memory (RAM). The depthof the RAM is given by the parameter ram_size. The internal memoryelements have a latch behavior (that is, they are level sensitive).The RAM has write and read operations. The write operation takesplace if the scalar input port oena is enabled (oena = 1). The readoperation takes place if the scalar input port iena is enabled (iena =1).In a write operation, the value of the input bus din is written to theaddress location specified by the value of the input bus addr.In a read operation, the value in the address location specified by addr is placed on the outputport dout. If the write operation is disabled, the output port dout goes to tristate mode.Even though read and write operations can be done simultaneously, it is not recommended.Because only one memory address can be accessed at any given time, a simultaneous operationmeans read and write to the same location.An internal RAM table is maintained. When write is not taking place, this table maintains itsvalue. If the value of the address port is greater than the value of ram_size, the scalar output portaddr_error is set to 1. In such cases, read or write operations do not take place. The RAMoperations are disabled if the address is out of range.The part has no timing control. Users are responsible for the timing control and to verify that thevalues on the input ports are retained for sufficient time. You need a good sequential memorycontroller for this part to work in a sequential design. We recommend that you do not synthesizethis part, because memory compilers perform much better than logic synthesis on memory parts.This is a non-synthesizable part. Even though synthesis tools can accept the code generated forthis part, you are advised not to synthesize this part.Functionram_table is a table of internal locations. The number of locations are given by the parameterram_size:ram_table(addr) = din if iena = 1. and addr < ram_sizedout= ram_table(addr) if oena = 1 and addr < ram_size= ZZ...otherwiseaddr_error = 0= 1if addr < ram_sizeotherwise212ModuleWare Reference Manual, Library Version 1.9September 18, 2008
Memory PartsSingle Port RAM (ram)ParametersTable 9-5. Single Port RAM ParametersParameter Values Defaultdin, dout, addr Port widths (must be > 0)Port widths (must be > 0)ram_size Number of memory locations in the RAM table 8AutomaticAutomaticDesign Rule Checks• An error is issued if the width of any port cannot be determined or if ports iena, oena andaddr_error do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports din, iena, oena,addr or dout are not connected.ModuleWare Reference Manual, Library Version 1.9 213September 18, 2008
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ModuleWare Reference Manualfor the
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Table of ContentsGated OR (or1) . .
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Table of ContentsBufif0 Primitive (
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List of TablesTable 5-18. N-Way Spl
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List of TablesTable 7-20. RS Flip-F
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List of TablesTable 10-41. XNOR Pri
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IntroductionNaming ConventionsNamin
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IntroductionSupported VHDL Packages
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IntroductionReset/Clear BehaviorYou
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IntroductionSet/Preset BehaviorSet/
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IntroductionGate BehaviorFunctioncl
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IntroductionEnable/Load BehaviorFun
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IntroductionVHDL Coding StyleNotes
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IntroductionDesign Rule CheckingFor
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IntroductionSlice SupportOtherwise
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Logic PartsN-Input AND Gate (and)N-
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Logic PartsN-Input XOR Gate (xor)N-
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Logic PartsN-Input NOR Gate (nor)N-
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Logic PartsAssign (assignment)Assig
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Logic PartsBit Setter (bitset)suffi
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Logic PartsBus Driver (busdrive)Bus
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Logic PartsGated OR (or1)Gated OR (
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Logic PartsInverter (inv)Inverter (
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Logic PartsReduction OR (tor)Reduct
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Logic PartsThree-state Buffer (trib
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Logic PartsThree-state bus (tribus)
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Logic PartsVariable Width N-Input A
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Logic PartsVariable Width N-Input X
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ConstantsConstant Value (constval)C
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ConstantsPower (vdd)Power (vdd)This
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Combine
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Combinatorial PartsEncoder (encoder
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Combinatorial PartsN-Input Multiple
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsW-Bit Multiplexe
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Combinatorial PartsW-Bit Multiplexe
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsBus Fill (wor
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Bit Manipulation PartsFixed Bit Sel
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Bit Manipulation PartsFixed Shifter
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Bit Manipulation PartsFixed Shifter
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Arithmetic Parts181 ALU (alu181)181
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Arithmetic Parts181 ALU (alu181)ovf
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Arithmetic PartsAbsolute Value (abs
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Arithmetic PartsAccumulator (acc)ad
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Arithmetic PartsAdder (add)Adder (a
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Arithmetic PartsAdder (add)Table 6-
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsComparator (cmp)Com
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Arithmetic PartsDecrementer (dec)De
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Arithmetic PartsIncrementer (inc)In
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsLeft Shifter (lshif
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Arithmetic PartsMultiplier (mult)A
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Arithmetic PartsRight Shifter (rshi
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Arithmetic PartsSubtractor (sub)Sub
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Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
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Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
Page 162 and 163: Register PartsT Flip-Flop (tff)Func
Page 164 and 165: Register PartsT Latch (tlatch)T Lat
Page 166 and 167: Register PartsT Latch (tlatch)Async
Page 168 and 169: Register PartsT Latch (tlatch)168Mo
Page 170 and 171: Sequential PartsBank of Flip-Flops
Page 172 and 173: Sequential PartsBank of Flip-Flops
Page 174 and 175: Sequential PartsBank of Latches (la
Page 176 and 177: Sequential PartsClock Divider (clkd
Page 178 and 179: Sequential PartsConfigurable Counte
Page 190 and 191: Sequential PartsModulo Counter (mod
Page 196 and 197: Sequential PartsParallel to Serial
Page 198 and 199: Sequential PartsParallel to Serial
Page 200 and 201: Sequential PartsSerial to Parallel
Page 202 and 203: Sequential PartsThree-state Bank of
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Page 206 and 207: Memory PartsDual Port RAM (ram2p)Du
Page 208 and 209: Memory PartsFirst In First Out (fif
Page 210 and 211: Memory PartsFirst In First Out (fif
Page 214 and 215: Memory PartsRegister File (regfile)
Page 216 and 217: Memory PartsROM (rom)ROM (rom)This
Page 218 and 219: Memory PartsROM (rom)The correspond
Page 220 and 221: Memory PartsROM (rom)Extended segme
Page 222 and 223: Memory PartsStack (stack)The reset
Page 224 and 225: Memory PartsStack (stack)Parameters
Page 226 and 227: Memory PartsSynthesizable Dual-Port
Page 228 and 229: Memory PartsSynthesizable Single-Po
Page 230 and 231: Primitive PartsIntroductionIntroduc
Page 232 and 233: Primitive PartsIntroductionTable 10
Page 234 and 235: Primitive PartsBuffer Primitive (pb
Page 236 and 237: Primitive PartsBufif0 Primitive (pb
Page 238 and 239: Primitive PartsBufif1 Primitive (pb
Page 240 and 241: Primitive PartsCMOS Primitive (pcmo
Page 242 and 243: Primitive PartsNAND Primitive (pnan
Page 244 and 245: Primitive PartsNOR Primitive (pnor)
Page 246 and 247: Primitive PartsNOT Primitive (pnot)
Page 248 and 249: Primitive PartsNotif0 Primitive (pn
Page 250 and 251: Primitive PartsNotif1 Primitive (pn
Page 252 and 253: Primitive PartsPMOS Primitive (ppmo
Page 254 and 255: Primitive PartsPullup Primitive (pp
Page 256 and 257: Primitive PartsRCMOS Primitive (prc
Page 258 and 259: Primitive PartsRPMOS Primitive (prp
Page 260 and 261: Primitive PartsXNOR Primitive (pxno
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Stimulus PartsSimple Clock (clk)Sim
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Stimulus PartsCompound Clock (cmpdc
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Stimulus PartsPulse (pulse)Pulse (p
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Stimulus PartsConstant Wave (constw
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Stimulus PartsRandom Value (random)
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Stimulus PartsRandom Value (random)
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Stimulus PartsCounter Value (counte
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Stimulus PartsCounter Value (counte
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Name ListName Description Pagedlatc
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Name ListName Description Pagesplit
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Function ListFunction Description P
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Function ListFunction Description P
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Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
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15. CONTROLLING LAW, JURISDICTION A
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ModuleWare Reference Guide - Hornad

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